{"id":"https://openalex.org/W2538802861","doi":"https://doi.org/10.1109/icecs.2003.1302039","title":"Modular energy recycling differential logic (MERDL) for low power application","display_name":"Modular energy recycling differential logic (MERDL) for low power application","publication_year":2004,"publication_date":"2004-06-03","ids":{"openalex":"https://openalex.org/W2538802861","doi":"https://doi.org/10.1109/icecs.2003.1302039","mag":"2538802861"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2003.1302039","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2003.1302039","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5079810808","display_name":"A. Abbasian","orcid":"https://orcid.org/0000-0002-9302-361X"},"institutions":[{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"A. Abbasian","raw_affiliation_strings":["IC Design Laboratory, Electrical and Computer Engineering Department, University of Tehran, Tehran, Iran"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IC Design Laboratory, Electrical and Computer Engineering Department, University of Tehran, Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087791851","display_name":"A.M. Nasri-Nasrabadi","orcid":null},"institutions":[{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"A.M. Nasri-Nasrabadi","raw_affiliation_strings":["IC Design Laboratory, Electrical and Computer Engineering Department, University of Tehran, Tehran, Iran"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IC Design Laboratory, Electrical and Computer Engineering Department, University of Tehran, Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5074063358","display_name":"Ali Afzali\u2010Kusha","orcid":"https://orcid.org/0000-0001-8614-2007"},"institutions":[{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"A. Afzali-Kusha","raw_affiliation_strings":["IC Design Laboratory, Electrical and Computer Engineering Department, University of Tehran, Tehran, Iran"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IC Design Laboratory, Electrical and Computer Engineering Department, University of Tehran, Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I23946033"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"1","issue":null,"first_page":"312","last_page":"315"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9966999888420105,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9902999997138977,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.7469074130058289},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.6738088130950928},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.6336593627929688},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5991338491439819},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.5950509309768677},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.594677209854126},{"id":"https://openalex.org/keywords/charge-sharing","display_name":"Charge sharing","score":0.5652771592140198},{"id":"https://openalex.org/keywords/logic-level","display_name":"Logic level","score":0.5635926127433777},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5596588253974915},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.5063031911849976},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.49498075246810913},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.49380454421043396},{"id":"https://openalex.org/keywords/energy","display_name":"Energy (signal processing)","score":0.4779496192932129},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4198474884033203},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4190079867839813},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.33315885066986084},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.30561232566833496},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.11624568700790405},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.09087416529655457},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.0851777195930481},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.06721559166908264}],"concepts":[{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.7469074130058289},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.6738088130950928},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.6336593627929688},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5991338491439819},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.5950509309768677},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.594677209854126},{"id":"https://openalex.org/C2781179661","wikidata":"https://www.wikidata.org/wiki/Q5074272","display_name":"Charge sharing","level":3,"score":0.5652771592140198},{"id":"https://openalex.org/C146569638","wikidata":"https://www.wikidata.org/wiki/Q173378","display_name":"Logic level","level":3,"score":0.5635926127433777},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5596588253974915},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.5063031911849976},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.49498075246810913},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.49380454421043396},{"id":"https://openalex.org/C186370098","wikidata":"https://www.wikidata.org/wiki/Q442787","display_name":"Energy (signal processing)","level":2,"score":0.4779496192932129},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4198474884033203},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4190079867839813},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.33315885066986084},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.30561232566833496},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.11624568700790405},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.09087416529655457},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.0851777195930481},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.06721559166908264},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs.2003.1302039","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2003.1302039","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8999999761581421,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1585996296","https://openalex.org/W1877294627","https://openalex.org/W2000260960","https://openalex.org/W2041767925","https://openalex.org/W2170619886","https://openalex.org/W6685057979"],"related_works":["https://openalex.org/W2082591327","https://openalex.org/W2108396794","https://openalex.org/W2171566066","https://openalex.org/W1593138522","https://openalex.org/W127821896","https://openalex.org/W2580743037","https://openalex.org/W2142702094","https://openalex.org/W2118487491","https://openalex.org/W2029162371","https://openalex.org/W1491122910"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"modular":[3],"energy":[4,32,50],"recycling":[5],"differential":[6],"logic":[7,81],"(MERDL).":[8],"MERDL":[9],"tries":[10],"to":[11,44,52],"achieve":[12],"power":[13,54,70,79],"efficiency":[14],"by":[15],"using":[16],"a":[17,61],"novel":[18],"charge":[19,24],"sharing":[20,25],"method.":[21],"In":[22,39],"traditional":[23],"methods,":[26],"half":[27],"of":[28,47,57,76],"the":[29,36,48,53,58,77],"output":[30,37],"capacitors'":[31],"was":[33],"lost":[34,49],"during":[35],"connection.":[38],"this":[40],"scheme":[41],"we":[42],"try":[43],"recycle":[45],"most":[46,78],"back":[51],"supply.":[55],"Implementation":[56],"idea":[59],"on":[60],"2-input":[62],"NAND":[63],"gate":[64],"showed":[65],"about":[66],"30%":[67],"improvement":[68],"in":[69],"delay":[71],"product":[72],"compared":[73],"with":[74],"one":[75],"efficient":[80],"styles":[82],"(i.e.":[83],"NCRCPL).":[84]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}