{"id":"https://openalex.org/W2541003462","doi":"https://doi.org/10.1109/icecs.2003.1302016","title":"Pipeline Event-driven No-race Charge recycling Logic (PENCL) for low power application","display_name":"Pipeline Event-driven No-race Charge recycling Logic (PENCL) for low power application","publication_year":2004,"publication_date":"2004-06-03","ids":{"openalex":"https://openalex.org/W2541003462","doi":"https://doi.org/10.1109/icecs.2003.1302016","mag":"2541003462"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2003.1302016","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2003.1302016","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5079810808","display_name":"A. Abbasian","orcid":"https://orcid.org/0000-0002-9302-361X"},"institutions":[{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]}],"countries":["IR"],"is_corresponding":true,"raw_author_name":"A. Abbasian","raw_affiliation_strings":["IC Design Laboratory, Electrical and Computer Engineering Department, University of Tehran, Iran"],"affiliations":[{"raw_affiliation_string":"IC Design Laboratory, Electrical and Computer Engineering Department, University of Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5074063358","display_name":"Ali Afzali\u2010Kusha","orcid":"https://orcid.org/0000-0001-8614-2007"},"institutions":[{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"A. Afzali-Kusha","raw_affiliation_strings":["IC Design Laboratory, Electrical and Computer Engineering Department, University of Tehran, Iran"],"affiliations":[{"raw_affiliation_string":"IC Design Laboratory, Electrical and Computer Engineering Department, University of Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5079810808"],"corresponding_institution_ids":["https://openalex.org/I23946033"],"apc_list":null,"apc_paid":null,"fwci":0.6583,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.74247867,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"1","issue":null,"first_page":"220","last_page":"223"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6951153874397278},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.6620773673057556},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.6595830917358398},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.6234652996063232},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.5586503148078918},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.5583587288856506},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5355313420295715},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.5160881876945496},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4808526635169983},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4782618284225464},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4700922966003418},{"id":"https://openalex.org/keywords/domino-logic","display_name":"Domino logic","score":0.425418496131897},{"id":"https://openalex.org/keywords/and-or-invert","display_name":"AND-OR-Invert","score":0.4193662405014038},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4139411747455597},{"id":"https://openalex.org/keywords/control-logic","display_name":"Control logic","score":0.4116045832633972},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.38881269097328186},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3617396950721741},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2805854082107544},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.2758915424346924},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.20578676462173462},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.17418888211250305}],"concepts":[{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6951153874397278},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.6620773673057556},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.6595830917358398},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.6234652996063232},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.5586503148078918},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.5583587288856506},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5355313420295715},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.5160881876945496},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4808526635169983},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4782618284225464},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4700922966003418},{"id":"https://openalex.org/C2777555262","wikidata":"https://www.wikidata.org/wiki/Q173391","display_name":"Domino logic","level":5,"score":0.425418496131897},{"id":"https://openalex.org/C130126468","wikidata":"https://www.wikidata.org/wiki/Q4652943","display_name":"AND-OR-Invert","level":5,"score":0.4193662405014038},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4139411747455597},{"id":"https://openalex.org/C2776350369","wikidata":"https://www.wikidata.org/wiki/Q843479","display_name":"Control logic","level":2,"score":0.4116045832633972},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.38881269097328186},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3617396950721741},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2805854082107544},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.2758915424346924},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.20578676462173462},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.17418888211250305},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs.2003.1302016","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2003.1302016","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8999999761581421,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320324891","display_name":"Iran Telecommunication Research Center","ror":"https://ror.org/01a3g2z22"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1585996296","https://openalex.org/W2000260960","https://openalex.org/W2041767925","https://openalex.org/W2167586194","https://openalex.org/W2170619886","https://openalex.org/W6685057979"],"related_works":["https://openalex.org/W2534190481","https://openalex.org/W2991771859","https://openalex.org/W2171918386","https://openalex.org/W2139625229","https://openalex.org/W2005207162","https://openalex.org/W2783353247","https://openalex.org/W321873635","https://openalex.org/W2158157809","https://openalex.org/W2136656113","https://openalex.org/W1702497178"],"abstract_inverted_index":{"A":[0],"novel":[1],"logic":[2,108],"family,":[3],"called":[4,109],"Pipeline":[5],"Event-driven":[6],"No-race":[7],"Charge":[8,114],"recycling":[9,55,115],"Logic":[10,116],"(PENCL),":[11],"has":[12,130],"been":[13],"proposed":[14],"and":[15],"analyzed.":[16],"PENCL":[17],"improves":[18],"power":[19,48,93,105],"efficiency":[20,58],"using":[21,65,87,95,127],"an":[22,31],"event":[23,32],"detector":[24],"circuit.":[25],"In":[26],"this":[27,96],"new":[28,61,97],"logic,":[29],"when":[30],"is":[33,124],"detected":[34],"on":[35],"the":[36,39,47,60,103,135],"input":[37],"signal,":[38],"outputs":[40],"are":[41],"connected.":[42],"This":[43,79],"technique":[44],"theoretically":[45],"reduces":[46],"consumption":[49],"50%":[50],"compared":[51,99],"to":[52,71,100],"conventional":[53],"charge":[54],"logic.":[56],"The":[57],"of":[59,102],"method":[62,98],"was":[63,81],"analyzed":[64],"seven":[66],"2-input":[67],"NAND":[68],"gates":[69],"connected":[70],"each":[72],"other":[73],"as":[74],"a":[75],"pipeline":[76],"modular":[77],"structure.":[78],"configuration":[80],"simulated":[82],"with":[83],"0.35/spl":[84],"mu/m":[85],"technology":[86],"HSPICE.":[88],"Simulation":[89],"results":[90],"show":[91],"43%":[92],"reduction":[94],"one":[101],"most":[104],"efficient":[106],"charge-recycling":[107],"race-Free":[110],"CMOS":[111],"Pass":[112],"gate":[113],"(FCPCL).":[117],"Dual":[118],"rail":[119],"isolated":[120],"latch":[121],"(DRIL),":[122],"which":[123],"introduced":[125],"for":[126],"in":[128],"PENCL,":[129],"much":[131],"better":[132],"performance":[133],"than":[134],"previous":[136],"static":[137],"latch.":[138]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}