{"id":"https://openalex.org/W2143046644","doi":"https://doi.org/10.1109/icecs.2002.1046242","title":"Shuffled serial adder: an area-latency effective serial adder","display_name":"Shuffled serial adder: an area-latency effective serial adder","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W2143046644","doi":"https://doi.org/10.1109/icecs.2002.1046242","mag":"2143046644"},"language":"en","primary_location":{"id":"doi:10.1109/icecs.2002.1046242","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2002.1046242","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"9th International Conference on Electronics, Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5010230701","display_name":"G.P. Saggese","orcid":null},"institutions":[{"id":"https://openalex.org/I71267560","display_name":"University of Naples Federico II","ror":"https://ror.org/05290cv24","country_code":"IT","type":"education","lineage":["https://openalex.org/I71267560"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"G.P. Saggese","raw_affiliation_strings":["Department of Electronics and Telecommunications Engineering, University of Naples-E2809CFederico IIE2809D, Napoli, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Telecommunications Engineering, University of Naples-E2809CFederico IIE2809D, Napoli, Italy","institution_ids":["https://openalex.org/I71267560"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058182656","display_name":"A.G.M. Strollo","orcid":"https://orcid.org/0000-0001-5737-1783"},"institutions":[{"id":"https://openalex.org/I71267560","display_name":"University of Naples Federico II","ror":"https://ror.org/05290cv24","country_code":"IT","type":"education","lineage":["https://openalex.org/I71267560"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"A.G.M. Strollo","raw_affiliation_strings":["Department of Electronics and Telecommunications Engineering, University of Naples-E2809CFederico IIE2809D, Napoli, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Telecommunications Engineering, University of Naples-E2809CFederico IIE2809D, Napoli, Italy","institution_ids":["https://openalex.org/I71267560"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045567395","display_name":"Nicola Mazzocca","orcid":"https://orcid.org/0000-0002-0401-9687"},"institutions":[{"id":"https://openalex.org/I197809005","display_name":"University of Campania \"Luigi Vanvitelli\"","ror":"https://ror.org/02kqnpp86","country_code":"IT","type":"education","lineage":["https://openalex.org/I197809005"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"N. Mazzocca","raw_affiliation_strings":["Department of Information Engineering, Second University of Naples, Caserta, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Information Engineering, Second University of Naples, Caserta, Italy","institution_ids":["https://openalex.org/I197809005"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5018481178","display_name":"Davide De","orcid":"https://orcid.org/0000-0003-0204-0949"},"institutions":[{"id":"https://openalex.org/I71267560","display_name":"University of Naples Federico II","ror":"https://ror.org/05290cv24","country_code":"IT","type":"education","lineage":["https://openalex.org/I71267560"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"D. De Caro","raw_affiliation_strings":["Department of Electronics and Telecommunications Engineering, University of Naples-E2809CFederico IIE2809D, Napoli, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Telecommunications Engineering, University of Naples-E2809CFederico IIE2809D, Napoli, Italy","institution_ids":["https://openalex.org/I71267560"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5010230701"],"corresponding_institution_ids":["https://openalex.org/I71267560"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.20472487,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"2","issue":null,"first_page":"607","last_page":"610"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.9485605955123901},{"id":"https://openalex.org/keywords/serial-binary-adder","display_name":"Serial binary adder","score":0.7258359789848328},{"id":"https://openalex.org/keywords/operand","display_name":"Operand","score":0.7145947217941284},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7132379412651062},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6866735816001892},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.6674419641494751},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.6320676803588867},{"id":"https://openalex.org/keywords/carry-save-adder","display_name":"Carry-save adder","score":0.6266089677810669},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5808039307594299},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3939463794231415},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.20401352643966675},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.12987029552459717},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07461249828338623}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.9485605955123901},{"id":"https://openalex.org/C116206932","wikidata":"https://www.wikidata.org/wiki/Q7454686","display_name":"Serial binary adder","level":4,"score":0.7258359789848328},{"id":"https://openalex.org/C55526617","wikidata":"https://www.wikidata.org/wiki/Q719375","display_name":"Operand","level":2,"score":0.7145947217941284},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7132379412651062},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6866735816001892},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.6674419641494751},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.6320676803588867},{"id":"https://openalex.org/C3227080","wikidata":"https://www.wikidata.org/wiki/Q5046770","display_name":"Carry-save adder","level":4,"score":0.6266089677810669},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5808039307594299},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3939463794231415},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.20401352643966675},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.12987029552459717},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07461249828338623}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecs.2002.1046242","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecs.2002.1046242","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"9th International Conference on Electronics, Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1976284552","https://openalex.org/W1993589577","https://openalex.org/W2057841079","https://openalex.org/W2097414281","https://openalex.org/W2102712964","https://openalex.org/W2131647018","https://openalex.org/W6644317693"],"related_works":["https://openalex.org/W2364181090","https://openalex.org/W4299002946","https://openalex.org/W2950518102","https://openalex.org/W2516396101","https://openalex.org/W2953746839","https://openalex.org/W2370097872","https://openalex.org/W2112595260","https://openalex.org/W2558076308","https://openalex.org/W2162004439","https://openalex.org/W4285082868"],"abstract_inverted_index":{"The":[0],"shuffled":[1],"adder,":[2,28],"a":[3,8,34,66,70],"novel":[4],"serial":[5,42],"adder":[6],"with":[7,48,104,107],"latency":[9],"proportional":[10],"to":[11,32,68,76],"log/sub":[12],"2/N,":[13],"where":[14],"N":[15,92],"is":[16,20,23,93],"the":[17,26,30,57,63,78,81,111,114],"operand":[18],"width,":[19],"presented.":[21],"It":[22,44],"derived":[24],"from":[25,56],"Kogge-Stone":[27],"reordering":[29],"cells":[31],"obtain":[33],"slice-based":[35],"structure":[36],"that":[37,60],"allows":[38],"an":[39],"area-time":[40,95],"effective":[41],"implementation.":[43],"can":[45],"be":[46],"fed":[47],"parallel":[49,53,71],"inputs":[50],"and":[51,75,102],"produce":[52],"outputs,":[54],"differently":[55],"digit-serial":[58,105],"approach":[59],"results":[61],"in":[62],"need":[64],"for":[65,88],"data-formatter":[67],"convert":[69],"input":[72],"into":[73],"digits,":[74],"collect":[77],"digits":[79],"of":[80,91,113],"output":[82],"word.":[83],"A":[84],"standard-cell":[85],"VLSI":[86],"implementation":[87],"different":[89],"values":[90],"presented:":[94],"performances":[96],"are":[97],"evaluated":[98],"through":[99],"circuit":[100],"simulations,":[101],"compared":[103],"adders":[106],"various":[108],"digit-size,":[109],"proving":[110],"attractiveness":[112],"proposed":[115],"structure.":[116]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}