{"id":"https://openalex.org/W2540350541","doi":"https://doi.org/10.1109/iceac.2013.6737645","title":"Power modeling and estimation during ADL-driven embedded processor design","display_name":"Power modeling and estimation during ADL-driven embedded processor design","publication_year":2013,"publication_date":"2013-12-01","ids":{"openalex":"https://openalex.org/W2540350541","doi":"https://doi.org/10.1109/iceac.2013.6737645","mag":"2540350541"},"language":"en","primary_location":{"id":"doi:10.1109/iceac.2013.6737645","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iceac.2013.6737645","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 4th Annual International Conference on Energy Aware Computing Systems and Applications (ICEAC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100401045","display_name":"Zheng Wang","orcid":"https://orcid.org/0000-0001-6157-0662"},"institutions":[{"id":"https://openalex.org/I887968799","display_name":"RWTH Aachen University","ror":"https://ror.org/04xfq0f34","country_code":"DE","type":"education","lineage":["https://openalex.org/I887968799"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Zheng Wang","raw_affiliation_strings":["MPSoC Architecture Research Group, RWTH-Aachen University, Aachen, Germany"],"affiliations":[{"raw_affiliation_string":"MPSoC Architecture Research Group, RWTH-Aachen University, Aachen, Germany","institution_ids":["https://openalex.org/I887968799"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100687371","display_name":"Lai Wang","orcid":"https://orcid.org/0000-0001-7262-0020"},"institutions":[{"id":"https://openalex.org/I887968799","display_name":"RWTH Aachen University","ror":"https://ror.org/04xfq0f34","country_code":"DE","type":"education","lineage":["https://openalex.org/I887968799"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Lai Wang","raw_affiliation_strings":["MPSoC Architecture Research Group, RWTH-Aachen University, Aachen, Germany"],"affiliations":[{"raw_affiliation_string":"MPSoC Architecture Research Group, RWTH-Aachen University, Aachen, Germany","institution_ids":["https://openalex.org/I887968799"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016211915","display_name":"Hui Xie","orcid":"https://orcid.org/0000-0001-7873-9399"},"institutions":[{"id":"https://openalex.org/I887968799","display_name":"RWTH Aachen University","ror":"https://ror.org/04xfq0f34","country_code":"DE","type":"education","lineage":["https://openalex.org/I887968799"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Hui Xie","raw_affiliation_strings":["MPSoC Architecture Research Group, RWTH-Aachen University, Aachen, Germany"],"affiliations":[{"raw_affiliation_string":"MPSoC Architecture Research Group, RWTH-Aachen University, Aachen, Germany","institution_ids":["https://openalex.org/I887968799"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5089860351","display_name":"Anupam Chattopadhyay","orcid":"https://orcid.org/0000-0002-8818-6983"},"institutions":[{"id":"https://openalex.org/I887968799","display_name":"RWTH Aachen University","ror":"https://ror.org/04xfq0f34","country_code":"DE","type":"education","lineage":["https://openalex.org/I887968799"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Anupam Chattopadhyay","raw_affiliation_strings":["MPSoC Architecture Research Group, RWTH-Aachen University, Aachen, Germany"],"affiliations":[{"raw_affiliation_string":"MPSoC Architecture Research Group, RWTH-Aachen University, Aachen, Germany","institution_ids":["https://openalex.org/I887968799"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5100401045"],"corresponding_institution_ids":["https://openalex.org/I887968799"],"apc_list":null,"apc_paid":null,"fwci":0.6304,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.72841711,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"250","issue":null,"first_page":"97","last_page":"102"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.748342752456665},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5831259489059448},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.5589466094970703},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.5397312641143799},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5107071995735168},{"id":"https://openalex.org/keywords/construct","display_name":"Construct (python library)","score":0.5040534734725952},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.5014965534210205},{"id":"https://openalex.org/keywords/processor-design","display_name":"Processor design","score":0.4835379123687744},{"id":"https://openalex.org/keywords/electronic-system-level-design-and-verification","display_name":"Electronic system-level design and verification","score":0.478056937456131},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.41871896386146545},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.41523227095603943},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.40058860182762146},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.23453810811042786},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.11471638083457947}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.748342752456665},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5831259489059448},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.5589466094970703},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.5397312641143799},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5107071995735168},{"id":"https://openalex.org/C2780801425","wikidata":"https://www.wikidata.org/wiki/Q5164392","display_name":"Construct (python library)","level":2,"score":0.5040534734725952},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.5014965534210205},{"id":"https://openalex.org/C526435321","wikidata":"https://www.wikidata.org/wiki/Q1303814","display_name":"Processor design","level":2,"score":0.4835379123687744},{"id":"https://openalex.org/C77495112","wikidata":"https://www.wikidata.org/wiki/Q5358436","display_name":"Electronic system-level design and verification","level":2,"score":0.478056937456131},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.41871896386146545},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.41523227095603943},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.40058860182762146},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.23453810811042786},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.11471638083457947},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iceac.2013.6737645","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iceac.2013.6737645","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 4th Annual International Conference on Energy Aware Computing Systems and Applications (ICEAC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8700000047683716,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1539883310","https://openalex.org/W1568759922","https://openalex.org/W2022665723","https://openalex.org/W2080498121","https://openalex.org/W2099315024","https://openalex.org/W2102727118","https://openalex.org/W2125018715","https://openalex.org/W2144293278","https://openalex.org/W2149532166","https://openalex.org/W2153974970","https://openalex.org/W2157435683","https://openalex.org/W2169826970","https://openalex.org/W2615865818","https://openalex.org/W3140903683","https://openalex.org/W4251095810","https://openalex.org/W6792941224"],"related_works":["https://openalex.org/W2156420848","https://openalex.org/W2543290882","https://openalex.org/W2085879890","https://openalex.org/W2269990635","https://openalex.org/W3168383044","https://openalex.org/W2137359677","https://openalex.org/W2159022270","https://openalex.org/W1603163876","https://openalex.org/W2133642747","https://openalex.org/W2125018715"],"abstract_inverted_index":{"Rising":[0],"concern":[1],"for":[2,87],"thermal":[3],"stress":[4],"and":[5,52,119],"tight":[6],"energy":[7],"constraints":[8],"have":[9],"forced":[10],"designers":[11],"to":[12,96,115],"consider":[13],"power":[14,28,37,50,85,100],"as":[15],"a":[16,33,106],"design":[17,21,43,113],"criterion":[18],"from":[19,74],"early":[20],"phase.":[22],"Despite":[23],"many":[24],"advances":[25],"in":[26,40],"high-level":[27,42,60,111],"estimation":[29,38,53],"techniques,":[30],"there":[31],"is":[32,67,81,94],"lack":[34],"of":[35,121],"generic":[36],"capabilities":[39],"prominent":[41],"flows.":[44],"In":[45],"this":[46],"paper":[47],"we":[48],"propose":[49],"modeling":[51,86],"techniques":[54],"during":[55],"Architecture":[56],"Description":[57],"Language":[58],"(ADL)-based":[59],"embedded":[61],"processor":[62,108,112],"design.":[63],"The":[64,78],"first":[65],"technique":[66,80],"based":[68],"on":[69,105],"accurate":[70],"switching":[71],"activity":[72],"extraction":[73],"cycle-accurate":[75],"instruction-set":[76],"simulation.":[77],"second":[79],"developed":[82],"through":[83],"unit-level":[84],"ADL":[88],"architecture":[89],"construct.":[90],"Multivariate":[91],"linear":[92],"regression":[93],"used":[95],"characterize":[97],"the":[98,117,122],"unit":[99],"model.":[101],"Experiments":[102],"are":[103],"performed":[104],"RISC":[107],"using":[109],"state-of-the-art":[110],"flow":[114],"demonstrate":[116],"accuracy":[118],"efficiency":[120],"proposed":[123],"techniques.":[124]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
