{"id":"https://openalex.org/W1966918226","doi":"https://doi.org/10.1109/icdsp.2013.6622742","title":"A high speed FPGA implementation of the 2D DCT for Ultra High Definition video coding","display_name":"A high speed FPGA implementation of the 2D DCT for Ultra High Definition video coding","publication_year":2013,"publication_date":"2013-07-01","ids":{"openalex":"https://openalex.org/W1966918226","doi":"https://doi.org/10.1109/icdsp.2013.6622742","mag":"1966918226"},"language":"en","primary_location":{"id":"doi:10.1109/icdsp.2013.6622742","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icdsp.2013.6622742","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 18th International Conference on Digital Signal Processing (DSP)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5082037558","display_name":"Paris Kitsos","orcid":"https://orcid.org/0000-0003-1851-8775"},"institutions":[{"id":"https://openalex.org/I1319660883","display_name":"Technological Educational Institute of Western Greece","ror":"https://ror.org/01mymm084","country_code":"GR","type":"education","lineage":["https://openalex.org/I1319660883"]}],"countries":["GR"],"is_corresponding":true,"raw_author_name":"Paris Kitsos","raw_affiliation_strings":["Department of Telecommunication Systems and Networks, Technological Educational Institute of Messolonghi, Greece","Dept. of Telecommun. Syst. & Networks, Technol. Educ. Inst. of Messolonghi, Greece"],"affiliations":[{"raw_affiliation_string":"Department of Telecommunication Systems and Networks, Technological Educational Institute of Messolonghi, Greece","institution_ids":["https://openalex.org/I1319660883"]},{"raw_affiliation_string":"Dept. of Telecommun. Syst. & Networks, Technol. Educ. Inst. of Messolonghi, Greece","institution_ids":["https://openalex.org/I1319660883"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048927560","display_name":"Nikolaos Voros","orcid":"https://orcid.org/0000-0003-2410-5205"},"institutions":[{"id":"https://openalex.org/I1319660883","display_name":"Technological Educational Institute of Western Greece","ror":"https://ror.org/01mymm084","country_code":"GR","type":"education","lineage":["https://openalex.org/I1319660883"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Nikolaos S. Voros","raw_affiliation_strings":["Department of Telecommunication Systems and Networks, Technological Educational Institute of Messolonghi, Greece","Dept. of Telecommun. Syst. & Networks, Technol. Educ. Inst. of Messolonghi, Greece"],"affiliations":[{"raw_affiliation_string":"Department of Telecommunication Systems and Networks, Technological Educational Institute of Messolonghi, Greece","institution_ids":["https://openalex.org/I1319660883"]},{"raw_affiliation_string":"Dept. of Telecommun. Syst. & Networks, Technol. Educ. Inst. of Messolonghi, Greece","institution_ids":["https://openalex.org/I1319660883"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5009483316","display_name":"Tasos Dagiuklas","orcid":"https://orcid.org/0000-0002-8101-1208"},"institutions":[{"id":"https://openalex.org/I231025917","display_name":"Hellenic Open University","ror":"https://ror.org/02kq26x23","country_code":"GR","type":"education","lineage":["https://openalex.org/I231025917"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Tasos Dagiuklas","raw_affiliation_strings":["Department of Computer Science, Hellenic Open University, Patras, Greece"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, Hellenic Open University, Patras, Greece","institution_ids":["https://openalex.org/I231025917"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5009555116","display_name":"Athanassios Skodras","orcid":"https://orcid.org/0000-0002-3872-4325"},"institutions":[{"id":"https://openalex.org/I174878644","display_name":"University of Patras","ror":"https://ror.org/017wvtq80","country_code":"GR","type":"education","lineage":["https://openalex.org/I174878644"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Athanassios N. Skodras","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Patras, Patras, Greece","Dept. of Electr. & Comput. Eng., Univ. OF PATRAS, Patras, Greece"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Patras, Patras, Greece","institution_ids":["https://openalex.org/I174878644"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Univ. OF PATRAS, Patras, Greece","institution_ids":["https://openalex.org/I174878644"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5082037558"],"corresponding_institution_ids":["https://openalex.org/I1319660883"],"apc_list":null,"apc_paid":null,"fwci":1.2926,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.7860118,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10741","display_name":"Video Coding and Compression Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10741","display_name":"Video Coding and Compression Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10901","display_name":"Advanced Data Compression Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8386993408203125},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7706402540206909},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.7507150173187256},{"id":"https://openalex.org/keywords/discrete-cosine-transform","display_name":"Discrete cosine transform","score":0.7166523933410645},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.5720801949501038},{"id":"https://openalex.org/keywords/coding","display_name":"Coding (social sciences)","score":0.5553659796714783},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.48622098565101624},{"id":"https://openalex.org/keywords/realization","display_name":"Realization (probability)","score":0.46328750252723694},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.421028196811676},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.41889631748199463},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4032042324542999},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4000563323497772},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.37656694650650024},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.19187051057815552},{"id":"https://openalex.org/keywords/image","display_name":"Image (mathematics)","score":0.1059335470199585},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.09712779521942139},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.07766962051391602},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.06915900111198425}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8386993408203125},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7706402540206909},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.7507150173187256},{"id":"https://openalex.org/C2221639","wikidata":"https://www.wikidata.org/wiki/Q2877","display_name":"Discrete cosine transform","level":3,"score":0.7166523933410645},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.5720801949501038},{"id":"https://openalex.org/C179518139","wikidata":"https://www.wikidata.org/wiki/Q5140297","display_name":"Coding (social sciences)","level":2,"score":0.5553659796714783},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.48622098565101624},{"id":"https://openalex.org/C2781089630","wikidata":"https://www.wikidata.org/wiki/Q21856745","display_name":"Realization (probability)","level":2,"score":0.46328750252723694},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.421028196811676},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.41889631748199463},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4032042324542999},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4000563323497772},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.37656694650650024},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.19187051057815552},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.1059335470199585},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.09712779521942139},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.07766962051391602},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.06915900111198425},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icdsp.2013.6622742","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icdsp.2013.6622742","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 18th International Conference on Digital Signal Processing (DSP)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.46000000834465027,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1487984166","https://openalex.org/W1916685473","https://openalex.org/W2058476306","https://openalex.org/W2095603848","https://openalex.org/W2105815873","https://openalex.org/W2106219841","https://openalex.org/W2111055683","https://openalex.org/W2140199336","https://openalex.org/W2146395539","https://openalex.org/W2158608042","https://openalex.org/W2172699263","https://openalex.org/W2332358012","https://openalex.org/W3003535879","https://openalex.org/W6773712673"],"related_works":["https://openalex.org/W3004362061","https://openalex.org/W4297665406","https://openalex.org/W2364622490","https://openalex.org/W2042515040","https://openalex.org/W2383986884","https://openalex.org/W2356141508","https://openalex.org/W1735031787","https://openalex.org/W2749962643","https://openalex.org/W281026211","https://openalex.org/W2390807153"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"two":[3],"high":[4],"performance":[5],"FPGA":[6,94],"architectures":[7,21,87],"for":[8,13,69,100],"the":[9,27,63,101],"2D":[10],"DCT":[11],"computation":[12],"Ultra":[14],"High":[15],"Definition":[16],"video":[17],"coding":[18],"systems.":[19],"Both":[20,86],"use":[22],"Distributed":[23],"Arithmetic":[24],"to":[25,41,52,78],"perform":[26],"necessary":[28],"multiplications":[29],"instead":[30],"of":[31,50,95,103],"traditional":[32],"multipliers.":[33],"The":[34],"first":[35],"architecture":[36],"uses":[37],"105":[38],"clock":[39],"cycles":[40,68],"transform":[42],"an":[43],"8\u00d78":[44,71],"block":[45,72],"and":[46,73],"reaches":[47],"a":[48,58,75],"rate":[49,76],"up":[51],"206":[53],"samples":[54,80],"per":[55,81],"second":[56,64,82],"at":[57,83],"338.5":[59],"MHz":[60],"frequency,":[61],"while":[62],"one":[65],"requires":[66],"65":[67],"each":[70],"achieves":[74],"equal":[77],"252":[79],"256":[84],"MHz.":[85],"have":[88],"been":[89,98],"implemented":[90],"using":[91],"VHDL.":[92],"Virtex7":[93],"Xilinx":[96],"has":[97],"used":[99],"realization":[102],"both":[104],"implementations.":[105]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":1}],"updated_date":"2026-03-25T13:04:00.132906","created_date":"2025-10-10T00:00:00"}