{"id":"https://openalex.org/W2149898070","doi":"https://doi.org/10.1109/icdsp.2011.6004926","title":"An FPGA implementation and performance evaluation of the seed block cipher","display_name":"An FPGA implementation and performance evaluation of the seed block cipher","publication_year":2011,"publication_date":"2011-07-01","ids":{"openalex":"https://openalex.org/W2149898070","doi":"https://doi.org/10.1109/icdsp.2011.6004926","mag":"2149898070"},"language":"en","primary_location":{"id":"doi:10.1109/icdsp.2011.6004926","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icdsp.2011.6004926","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 17th International Conference on Digital Signal Processing (DSP)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5082037558","display_name":"Paris Kitsos","orcid":"https://orcid.org/0000-0003-1851-8775"},"institutions":[{"id":"https://openalex.org/I231025917","display_name":"Hellenic Open University","ror":"https://ror.org/02kq26x23","country_code":"GR","type":"education","lineage":["https://openalex.org/I231025917"]}],"countries":["GR"],"is_corresponding":true,"raw_author_name":"Paris Kitsos","raw_affiliation_strings":["Computer Science, Hellenic Open University, Greece"],"affiliations":[{"raw_affiliation_string":"Computer Science, Hellenic Open University, Greece","institution_ids":["https://openalex.org/I231025917"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5009555116","display_name":"Athanassios Skodras","orcid":"https://orcid.org/0000-0002-3872-4325"},"institutions":[{"id":"https://openalex.org/I231025917","display_name":"Hellenic Open University","ror":"https://ror.org/02kq26x23","country_code":"GR","type":"education","lineage":["https://openalex.org/I231025917"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Athanassios N. Skodras","raw_affiliation_strings":["Computer Science, Hellenic Open University, Greece"],"affiliations":[{"raw_affiliation_string":"Computer Science, Hellenic Open University, Greece","institution_ids":["https://openalex.org/I231025917"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5082037558"],"corresponding_institution_ids":["https://openalex.org/I231025917"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.16200046,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7827980518341064},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7784816026687622},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.7267978191375732},{"id":"https://openalex.org/keywords/block-cipher","display_name":"Block cipher","score":0.6324830055236816},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.565520167350769},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5083767771720886},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.5061301589012146},{"id":"https://openalex.org/keywords/logic-block","display_name":"Logic block","score":0.49425816535949707},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.4556456506252289},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4538511037826538},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.4482934772968292},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.4262332022190094},{"id":"https://openalex.org/keywords/encryption","display_name":"Encryption","score":0.37025922536849976},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.12786728143692017},{"id":"https://openalex.org/keywords/wireless","display_name":"Wireless","score":0.12334877252578735},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.11601155996322632},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1099204421043396}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7827980518341064},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7784816026687622},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.7267978191375732},{"id":"https://openalex.org/C106544461","wikidata":"https://www.wikidata.org/wiki/Q543151","display_name":"Block cipher","level":3,"score":0.6324830055236816},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.565520167350769},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5083767771720886},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.5061301589012146},{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.49425816535949707},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.4556456506252289},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4538511037826538},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.4482934772968292},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.4262332022190094},{"id":"https://openalex.org/C148730421","wikidata":"https://www.wikidata.org/wiki/Q141090","display_name":"Encryption","level":2,"score":0.37025922536849976},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.12786728143692017},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.12334877252578735},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.11601155996322632},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1099204421043396},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icdsp.2011.6004926","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icdsp.2011.6004926","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 17th International Conference on Digital Signal Processing (DSP)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4099999964237213,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1591098212","https://openalex.org/W1815098404","https://openalex.org/W2101980633","https://openalex.org/W2113026691","https://openalex.org/W2166009017","https://openalex.org/W2289151340","https://openalex.org/W6805997092"],"related_works":["https://openalex.org/W2110818533","https://openalex.org/W1917852300","https://openalex.org/W2384838054","https://openalex.org/W2139058049","https://openalex.org/W2376018793","https://openalex.org/W2548456620","https://openalex.org/W2911649771","https://openalex.org/W2148697719","https://openalex.org/W2070083638","https://openalex.org/W2075214143"],"abstract_inverted_index":{"An":[0],"FPGA":[1,81],"implementation":[2,53],"of":[3,38,48,58],"the":[4,36,39,46,75,78],"128-bit":[5],"SEED":[6],"block":[7],"cipher":[8,49],"is":[9,42],"presented":[10],"in":[11],"this":[12,34],"paper.":[13],"The":[14,51,66],"proposed":[15,52],"architecture":[16],"achieves":[17],"high-speed":[18],"with":[19,29],"little":[20],"hardware":[21,76],"resources":[22],"using":[23,70],"feedback":[24],"logic":[25],"and":[26,73],"inner":[27],"pipeline":[28],"negative":[30],"edge-triggered":[31],"registers.":[32],"In":[33],"way,":[35],"delay":[37],"critical":[40],"path":[41],"reduced,":[43],"without":[44],"increasing":[45],"latency":[47],"execution.":[50],"reaches":[54],"a":[55],"data":[56],"throughput":[57],"369.6":[59],"Mbps":[60],"at":[61],"46.2":[62],"MHz":[63],"clock":[64],"frequency.":[65],"design":[67],"was":[68,83],"coded":[69],"VHDL":[71],"language":[72],"for":[74],"implementation,":[77],"Xilinx":[79],"Spartan-3A":[80],"device":[82],"used.":[84]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}