{"id":"https://openalex.org/W4206411238","doi":"https://doi.org/10.1109/icct52962.2021.9657879","title":"Design and Implementation of DSP Cache","display_name":"Design and Implementation of DSP Cache","publication_year":2021,"publication_date":"2021-10-13","ids":{"openalex":"https://openalex.org/W4206411238","doi":"https://doi.org/10.1109/icct52962.2021.9657879"},"language":"en","primary_location":{"id":"doi:10.1109/icct52962.2021.9657879","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icct52962.2021.9657879","pdf_url":null,"source":{"id":"https://openalex.org/S4363607878","display_name":"2021 IEEE 21st International Conference on Communication Technology (ICCT)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE 21st International Conference on Communication Technology (ICCT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5052955760","display_name":"Kunkun Liang","orcid":null},"institutions":[{"id":"https://openalex.org/I116953780","display_name":"Tongji University","ror":"https://ror.org/03rc6as71","country_code":"CN","type":"education","lineage":["https://openalex.org/I116953780"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Kunkun Liang","raw_affiliation_strings":["Electronics and Information Engineering College Key Laboratory of Embedded System and Service Computing, Ministry of Education, Tongji University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Electronics and Information Engineering College Key Laboratory of Embedded System and Service Computing, Ministry of Education, Tongji University, Shanghai, China","institution_ids":["https://openalex.org/I116953780"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075806425","display_name":"Jun Wu","orcid":"https://orcid.org/0000-0001-7090-8653"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jun Wu","raw_affiliation_strings":["School of Computer Science, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"School of Computer Science, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109282564","display_name":"Haoqi Ren","orcid":null},"institutions":[{"id":"https://openalex.org/I116953780","display_name":"Tongji University","ror":"https://ror.org/03rc6as71","country_code":"CN","type":"education","lineage":["https://openalex.org/I116953780"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Haoqi Ren","raw_affiliation_strings":["Electronics and Information Engineering College Key Laboratory of Embedded System and Service Computing, Ministry of Education, Tongji University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Electronics and Information Engineering College Key Laboratory of Embedded System and Service Computing, Ministry of Education, Tongji University, Shanghai, China","institution_ids":["https://openalex.org/I116953780"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100444211","display_name":"Zhifeng Zhang","orcid":"https://orcid.org/0000-0001-7333-3779"},"institutions":[{"id":"https://openalex.org/I116953780","display_name":"Tongji University","ror":"https://ror.org/03rc6as71","country_code":"CN","type":"education","lineage":["https://openalex.org/I116953780"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhifeng Zhang","raw_affiliation_strings":["Electronics and Information Engineering College Key Laboratory of Embedded System and Service Computing, Ministry of Education, Tongji University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Electronics and Information Engineering College Key Laboratory of Embedded System and Service Computing, Ministry of Education, Tongji University, Shanghai, China","institution_ids":["https://openalex.org/I116953780"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5060850220","display_name":"Bin Tan","orcid":null},"institutions":[{"id":"https://openalex.org/I14748160","display_name":"Jinggangshan University","ror":"https://ror.org/04exd0a76","country_code":"CN","type":"education","lineage":["https://openalex.org/I14748160"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Bin Tan","raw_affiliation_strings":["College of Electronics and Information Engineering, Jinggangshan University, Ji'an, China"],"affiliations":[{"raw_affiliation_string":"College of Electronics and Information Engineering, Jinggangshan University, Ji'an, China","institution_ids":["https://openalex.org/I14748160"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5052955760"],"corresponding_institution_ids":["https://openalex.org/I116953780"],"apc_list":null,"apc_paid":null,"fwci":0.4363,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.51460081,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"11","issue":null,"first_page":"993","last_page":"997"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12941","display_name":"Embedded Systems and FPGA Design","score":0.9854999780654907,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12941","display_name":"Embedded Systems and FPGA Design","score":0.9854999780654907,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11269","display_name":"Algorithms and Data Compression","score":0.9812999963760376,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.97079998254776,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.7094246745109558},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7076346278190613},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.6362497806549072},{"id":"https://openalex.org/keywords/smart-cache","display_name":"Smart Cache","score":0.4303879141807556},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.4083382785320282},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3820493817329407},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.35354939103126526},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.33027034997940063},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.29512181878089905},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.19828525185585022}],"concepts":[{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.7094246745109558},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7076346278190613},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.6362497806549072},{"id":"https://openalex.org/C167713795","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"Smart Cache","level":5,"score":0.4303879141807556},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.4083382785320282},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3820493817329407},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.35354939103126526},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.33027034997940063},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.29512181878089905},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.19828525185585022}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icct52962.2021.9657879","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icct52962.2021.9657879","pdf_url":null,"source":{"id":"https://openalex.org/S4363607878","display_name":"2021 IEEE 21st International Conference on Communication Technology (ICCT)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE 21st International Conference on Communication Technology (ICCT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8600000143051147,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W2071311378","https://openalex.org/W2265111614","https://openalex.org/W2761296247","https://openalex.org/W2892335136","https://openalex.org/W3004107650","https://openalex.org/W3111801817","https://openalex.org/W4231456514"],"related_works":["https://openalex.org/W2031173804","https://openalex.org/W2114386333","https://openalex.org/W2509523906","https://openalex.org/W2363769136","https://openalex.org/W2148571123","https://openalex.org/W3085471909","https://openalex.org/W2041820064","https://openalex.org/W198173854","https://openalex.org/W2404820046","https://openalex.org/W2324141783"],"abstract_inverted_index":{"The":[0,99,153],"cache":[1,23,103,131,134,158],"can":[2,104],"improve":[3],"the":[4,14,31,39,43,53,58,83,102,125,130,133,138,157,163,171],"DSP":[5,46,59],"processor's":[6],"access":[7,33,97],"speed":[8],"to":[9,92,109,113],"external":[10],"memory":[11,32],"and":[12,21,35,72,77,87,120,147,162],"solve":[13],"\u201cStorage":[15],"Wall\u201d":[16],"problem.":[17],"Designing":[18],"an":[19,26],"efficient":[20],"flexible":[22],"module":[24,89],"plays":[25],"vital":[27],"role":[28],"in":[29,67,129],"improving":[30],"efficiency":[34],"overall":[36],"performance":[37],"of":[38,45,57,101,173],"DSP.":[40],"Based":[41],"on":[42],"analysis":[44],"storage":[47],"level":[48,75],"design":[49,71],"requirements,":[50],"combined":[51],"with":[52],"actual":[54,110],"pipeline":[55],"structure":[56],"processor":[60],"SWIFT":[61],"independently":[62],"developed":[63],"by":[64],"our":[65],"laboratory,":[66],"this":[68],"paper,":[69],"we":[70],"implement":[73],"first-":[74],"instruction":[76,140],"data":[78,127],"cache.":[79],"For":[80],"L1":[81],"D-Cache,":[82],"relevant":[84],"conflict":[85],"detection":[86],"processing":[88],"is":[90,136,141],"designed":[91],"support":[93],"four":[94],"parallel":[95],"Load/Store":[96],"requests.":[98],"size":[100,135],"be":[105],"flexibly":[106],"configured":[107],"according":[108],"application":[111],"requirements":[112],"achieve":[114],"a":[115],"balance":[116],"between":[117],"power":[118],"consumption":[119],"latency.":[121],"To":[122],"write":[123],"back":[124],"modified":[126],"left":[128],"before":[132],"changed,":[137],"Cacheclean":[139],"designed.":[142],"Finally,":[143],"module-level":[144],"functional":[145],"verification":[146],"logic":[148,167],"synthesis":[149,168],"are":[150],"carried":[151],"out.":[152],"results":[154],"show":[155],"that":[156],"function":[159],"meets":[160,170],"expectations,":[161],"critical":[164],"path":[165],"after":[166],"optimization":[169],"requirement":[172],"1GHz":[174],"frenuency.":[175]},"counts_by_year":[{"year":2023,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}