{"id":"https://openalex.org/W4403060675","doi":"https://doi.org/10.1109/iccsce61582.2024.10696692","title":"Analysis of Logic Synthesis Results with various Technology Nodes for RISC-V Design","display_name":"Analysis of Logic Synthesis Results with various Technology Nodes for RISC-V Design","publication_year":2024,"publication_date":"2024-08-23","ids":{"openalex":"https://openalex.org/W4403060675","doi":"https://doi.org/10.1109/iccsce61582.2024.10696692"},"language":"en","primary_location":{"id":"doi:10.1109/iccsce61582.2024.10696692","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccsce61582.2024.10696692","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IEEE 14th International Conference on Control System, Computing and Engineering (ICCSCE)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5068426200","display_name":"Siu Hong Loh","orcid":"https://orcid.org/0000-0002-4192-1477"},"institutions":[{"id":"https://openalex.org/I931681460","display_name":"Universiti Tunku Abdul Rahman","ror":"https://ror.org/050pq4m56","country_code":"MY","type":"education","lineage":["https://openalex.org/I931681460"]}],"countries":["MY"],"is_corresponding":true,"raw_author_name":"Siu Hong Loh","raw_affiliation_strings":["Universiti Tunku Abdul Rahman,Kampar,Malaysia"],"affiliations":[{"raw_affiliation_string":"Universiti Tunku Abdul Rahman,Kampar,Malaysia","institution_ids":["https://openalex.org/I931681460"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5107696944","display_name":"Yenn Nee Koay","orcid":null},"institutions":[{"id":"https://openalex.org/I931681460","display_name":"Universiti Tunku Abdul Rahman","ror":"https://ror.org/050pq4m56","country_code":"MY","type":"education","lineage":["https://openalex.org/I931681460"]}],"countries":["MY"],"is_corresponding":false,"raw_author_name":"Yenn Nee Koay","raw_affiliation_strings":["Universiti Tunku Abdul Rahman,Kampar,Malaysia"],"affiliations":[{"raw_affiliation_string":"Universiti Tunku Abdul Rahman,Kampar,Malaysia","institution_ids":["https://openalex.org/I931681460"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041305483","display_name":"Kim Ho Yeap","orcid":"https://orcid.org/0000-0001-7043-649X"},"institutions":[{"id":"https://openalex.org/I931681460","display_name":"Universiti Tunku Abdul Rahman","ror":"https://ror.org/050pq4m56","country_code":"MY","type":"education","lineage":["https://openalex.org/I931681460"]}],"countries":["MY"],"is_corresponding":false,"raw_author_name":"Kim Ho Yeap","raw_affiliation_strings":["Universiti Tunku Abdul Rahman,Kampar,Malaysia"],"affiliations":[{"raw_affiliation_string":"Universiti Tunku Abdul Rahman,Kampar,Malaysia","institution_ids":["https://openalex.org/I931681460"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5091602157","display_name":"Jia Jia Sim","orcid":null},"institutions":[{"id":"https://openalex.org/I931681460","display_name":"Universiti Tunku Abdul Rahman","ror":"https://ror.org/050pq4m56","country_code":"MY","type":"education","lineage":["https://openalex.org/I931681460"]}],"countries":["MY"],"is_corresponding":false,"raw_author_name":"Jia Jia Sim","raw_affiliation_strings":["Universiti Tunku Abdul Rahman,Kampar,Malaysia"],"affiliations":[{"raw_affiliation_string":"Universiti Tunku Abdul Rahman,Kampar,Malaysia","institution_ids":["https://openalex.org/I931681460"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5068426200"],"corresponding_institution_ids":["https://openalex.org/I931681460"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.1716437,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"100","last_page":"105"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9933000206947327,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9933000206947327,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9854999780654907,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9664999842643738,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6544286012649536},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5852903127670288},{"id":"https://openalex.org/keywords/reduced-instruction-set-computing","display_name":"Reduced instruction set computing","score":0.5300376415252686},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.49557554721832275},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3973577618598938},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.35444265604019165},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.12943291664123535},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.1262841820716858}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6544286012649536},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5852903127670288},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.5300376415252686},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.49557554721832275},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3973577618598938},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.35444265604019165},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.12943291664123535},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.1262841820716858}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccsce61582.2024.10696692","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccsce61582.2024.10696692","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IEEE 14th International Conference on Control System, Computing and Engineering (ICCSCE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1626344417","https://openalex.org/W2539499348","https://openalex.org/W2969280549","https://openalex.org/W3088945985","https://openalex.org/W3199828306","https://openalex.org/W4308407499","https://openalex.org/W4310927849","https://openalex.org/W4390660438"],"related_works":["https://openalex.org/W2035206467","https://openalex.org/W2512308948","https://openalex.org/W2068921804","https://openalex.org/W2098419840","https://openalex.org/W4387696986","https://openalex.org/W1966764473","https://openalex.org/W2130565894","https://openalex.org/W1944377106","https://openalex.org/W2901661247","https://openalex.org/W4312497944"],"abstract_inverted_index":{"This":[0,57,157],"study":[1],"investigates":[2],"the":[3,36,43,51,62,67,91,95,102,128,168],"synthesis":[4],"process":[5],"of":[6,39,66,101,127],"a":[7,108],"RISC-V":[8,44,52,103],"processor":[9,40,104,129,151],"with":[10],"varying":[11],"technology":[12,88,121,149],"nodes":[13,122],"($14":[14],"\\mathrm{~nm},":[15],"32":[16],"\\mathrm{~nm}$,":[17],"and":[18,21,82,117],"90":[19],"nm)":[20],"clock":[22,78,114,134],"periods":[23],"ranging":[24],"from":[25],"0":[26],"to":[27,34,61,86,136,144,163],"5":[28],"nanoseconds.":[29],"The":[30,69],"problem":[31],"statement":[32],"is":[33,54,59,105,130,154],"address":[35],"limited":[37],"availability":[38],"designs":[41,146],"using":[42],"ISA":[45],"in":[46],"undergraduate":[47,169],"study,":[48],"even":[49],"though":[50],"community":[53],"growing":[55],"rapidly.":[56],"shortage":[58],"due":[60],"relatively":[63],"recent":[64],"development":[65],"ISA.":[68],"analysis":[70],"initiates":[71],"by":[72],"considering":[73],"design":[74,165],"constraints,":[75],"such":[76],"as":[77],"frequency,":[79],"area":[80,152],"limitations,":[81],"timing":[83],"requisites":[84],"specific":[85],"each":[87,148],"node.":[89],"Utilizing":[90],"Design":[92],"Compiler":[93],"tool,":[94],"Register":[96],"Transfer":[97],"Level":[98],"(RTL)":[99],"description":[100],"transformed":[106],"into":[107,139],"gate-level":[109],"netlist.":[110],"Performance":[111],"metrics":[112],"including":[113],"period":[115],"requirements,":[116],"slack":[118],"margins":[119],"across":[120],"are":[123],"scrutinized.":[124],"Power":[125],"consumption":[126,153],"assessed":[131],"at":[132,167],"various":[133],"intervals":[135],"gain":[137],"insights":[138],"its":[140],"power":[141],"profile.":[142],"Additionally,":[143],"enhance":[145],"for":[147],"node,":[150],"thoroughly":[155],"examined.":[156],"paper":[158],"delineates":[159],"an":[160],"approach":[161],"applicable":[162],"VLSI":[164],"courses":[166],"level.":[170]},"counts_by_year":[],"updated_date":"2025-12-21T01:58:51.020947","created_date":"2025-10-10T00:00:00"}