{"id":"https://openalex.org/W2046530291","doi":"https://doi.org/10.1109/iccsce.2014.7072752","title":"A comparative study on the implementation of reversible Binary Coded Decimal (BCD) Adder performance on Field Programmable Gate array (FPGA)","display_name":"A comparative study on the implementation of reversible Binary Coded Decimal (BCD) Adder performance on Field Programmable Gate array (FPGA)","publication_year":2014,"publication_date":"2014-11-01","ids":{"openalex":"https://openalex.org/W2046530291","doi":"https://doi.org/10.1109/iccsce.2014.7072752","mag":"2046530291"},"language":"en","primary_location":{"id":"doi:10.1109/iccsce.2014.7072752","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccsce.2014.7072752","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE International Conference on Control System, Computing and Engineering (ICCSCE 2014)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5048560315","display_name":"Nyap Tet Clement Tham","orcid":null},"institutions":[{"id":"https://openalex.org/I158949172","display_name":"Curtin University Sarawak","ror":"https://ror.org/024fm2y42","country_code":"MY","type":"education","lineage":["https://openalex.org/I158949172"]}],"countries":["MY"],"is_corresponding":true,"raw_author_name":"Nyap Tet Clement Tham","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Curtin University Sarawak, Miri, Malaysia","Department of Electrical and Computer Engineering, Curtin University (Sarawak), Miri, Malaysia"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Curtin University Sarawak, Miri, Malaysia","institution_ids":["https://openalex.org/I158949172"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Curtin University (Sarawak), Miri, Malaysia","institution_ids":["https://openalex.org/I158949172"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057753946","display_name":"Alpha Agape Gopalaiy","orcid":null},"institutions":[{"id":"https://openalex.org/I11662577","display_name":"Monash University Malaysia","ror":"https://ror.org/00yncr324","country_code":"MY","type":"education","lineage":["https://openalex.org/I11662577"]}],"countries":["MY"],"is_corresponding":false,"raw_author_name":"Alpha Agape Gopalaiy","raw_affiliation_strings":["Department of Mechatronics Engineering, Monash University Malaysia, Bandar Sunway, Selangor, Malaysia"],"affiliations":[{"raw_affiliation_string":"Department of Mechatronics Engineering, Monash University Malaysia, Bandar Sunway, Selangor, Malaysia","institution_ids":["https://openalex.org/I11662577"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010309105","display_name":"Lenin Gopal","orcid":"https://orcid.org/0000-0002-8302-0458"},"institutions":[{"id":"https://openalex.org/I158949172","display_name":"Curtin University Sarawak","ror":"https://ror.org/024fm2y42","country_code":"MY","type":"education","lineage":["https://openalex.org/I158949172"]}],"countries":["MY"],"is_corresponding":false,"raw_author_name":"Lenin Gopal","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Curtin University Sarawak Miri, Malaysia","Department of Electrical and Computer Engineering, Curtin University (Sarawak), Miri, Malaysia"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Curtin University Sarawak Miri, Malaysia","institution_ids":["https://openalex.org/I158949172"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Curtin University (Sarawak), Miri, Malaysia","institution_ids":["https://openalex.org/I158949172"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5013082893","display_name":"Ashutosh Kumar Singh","orcid":"https://orcid.org/0000-0002-8053-5050"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Ashutosh K. Singh","raw_affiliation_strings":["Department of Computer Applications NIT urukshetra, Haryana, India"],"affiliations":[{"raw_affiliation_string":"Department of Computer Applications NIT urukshetra, Haryana, India","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5048560315"],"corresponding_institution_ids":["https://openalex.org/I158949172"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.09797297,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":"84","issue":null,"first_page":"399","last_page":"404"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10682","display_name":"Quantum Computing Algorithms and Architecture","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.9556738138198853},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8512657880783081},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7405122518539429},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.584261417388916},{"id":"https://openalex.org/keywords/decimal","display_name":"Decimal","score":0.5034465193748474},{"id":"https://openalex.org/keywords/serial-binary-adder","display_name":"Serial binary adder","score":0.4743056297302246},{"id":"https://openalex.org/keywords/carry-save-adder","display_name":"Carry-save adder","score":0.4708399772644043},{"id":"https://openalex.org/keywords/binary-number","display_name":"Binary number","score":0.4684073328971863},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.4518829584121704},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.4062706530094147},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3209663927555084},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.11001303791999817},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.058644771575927734},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.05847728252410889}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.9556738138198853},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8512657880783081},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7405122518539429},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.584261417388916},{"id":"https://openalex.org/C65045869","wikidata":"https://www.wikidata.org/wiki/Q81365","display_name":"Decimal","level":2,"score":0.5034465193748474},{"id":"https://openalex.org/C116206932","wikidata":"https://www.wikidata.org/wiki/Q7454686","display_name":"Serial binary adder","level":4,"score":0.4743056297302246},{"id":"https://openalex.org/C3227080","wikidata":"https://www.wikidata.org/wiki/Q5046770","display_name":"Carry-save adder","level":4,"score":0.4708399772644043},{"id":"https://openalex.org/C48372109","wikidata":"https://www.wikidata.org/wiki/Q3913","display_name":"Binary number","level":2,"score":0.4684073328971863},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.4518829584121704},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.4062706530094147},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3209663927555084},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.11001303791999817},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.058644771575927734},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.05847728252410889}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iccsce.2014.7072752","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccsce.2014.7072752","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE International Conference on Control System, Computing and Engineering (ICCSCE 2014)","raw_type":"proceedings-article"},{"id":"pmh:oai:espace.curtin.edu.au:20.500.11937/29437","is_oa":false,"landing_page_url":"http://hdl.handle.net/20.500.11937/29437","pdf_url":null,"source":{"id":"https://openalex.org/S4306401790","display_name":"eSpace (Curtin University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205640436","host_organization_name":"Curtin University","host_organization_lineage":["https://openalex.org/I205640436"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Conference Paper"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.41999998688697815,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":36,"referenced_works":["https://openalex.org/W1577706195","https://openalex.org/W1631356911","https://openalex.org/W1964076093","https://openalex.org/W1974596145","https://openalex.org/W1983246068","https://openalex.org/W2003989103","https://openalex.org/W2012206667","https://openalex.org/W2025516544","https://openalex.org/W2026604635","https://openalex.org/W2041607314","https://openalex.org/W2044853026","https://openalex.org/W2047495519","https://openalex.org/W2051464839","https://openalex.org/W2059041305","https://openalex.org/W2068967633","https://openalex.org/W2073226131","https://openalex.org/W2078540024","https://openalex.org/W2105259569","https://openalex.org/W2119953332","https://openalex.org/W2135747429","https://openalex.org/W2149904950","https://openalex.org/W2156355982","https://openalex.org/W2162383260","https://openalex.org/W2188570344","https://openalex.org/W2314449761","https://openalex.org/W2551390228","https://openalex.org/W2764347725","https://openalex.org/W2912120411","https://openalex.org/W3123104598","https://openalex.org/W3203992401","https://openalex.org/W4233798822","https://openalex.org/W4251109627","https://openalex.org/W6656594533","https://openalex.org/W6686950604","https://openalex.org/W6699053159","https://openalex.org/W6759099555"],"related_works":["https://openalex.org/W2364181090","https://openalex.org/W4299002946","https://openalex.org/W2950518102","https://openalex.org/W2516396101","https://openalex.org/W2953746839","https://openalex.org/W2370097872","https://openalex.org/W2112595260","https://openalex.org/W4295540194","https://openalex.org/W2064215635","https://openalex.org/W986131379"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3],"present":[4],"a":[5,40,66,92],"performance":[6],"comparison":[7],"of":[8,45,69,79,91,116],"Binary":[9],"Coded":[10],"Decimal":[11],"(BCD)":[12],"Adders":[13],"on":[14,36,135,149,158],"Field":[15],"Programmable":[16],"Gate":[17],"Logic":[18],"(FPGA)":[19],"for":[20,42],"functional":[21,43],"and":[22,74,83,124,127,141,156,162],"behavioural":[23],"verification.":[24],"Although":[25],"it":[26],"does":[27],"not":[28],"prove":[29],"that":[30],"the":[31,80],"circuit":[32,52],"is":[33],"reversible,":[34],"implementation":[35,90],"FPGA":[37],"serves":[38],"as":[39,72,77],"platform":[41],"verification":[44],"circuits.":[46],"BCD":[47,60,93,113],"adders":[48,61],"are":[49,85,146],"one":[50],"such":[51,71],"which":[53],"has":[54,95],"gain":[55],"wide":[56,67],"research":[57],"emphasis":[58],"where":[59],"can":[62],"be":[63],"implemented":[64,148],"in":[65,86,111],"array":[68],"applications":[70],"financial":[73],"commercial":[75],"computations":[76],"most":[78],"data":[81],"stored":[82],"calculated":[84],"decimal":[87],"format.":[88],"Hardware":[89,153],"adder":[94,114],"been":[96],"known":[97],"to":[98],"perform":[99],"at":[100],"least":[101],"100":[102],"times":[103],"faster":[104],"than":[105],"its":[106],"software":[107],"counterparts.":[108],"Current":[109],"trends":[110],"reversible":[112],"consist":[115],"4":[117],"major":[118],"parts":[119],"\u2014":[120],"4-bit":[121,129],"Adder,":[122],"Correction":[123],"Detection":[125],"Unit,":[126],"Modified":[128],"Adder.":[130],"Designs":[131],"were":[132],"chosen":[133],"based":[134],"overall":[136],"design":[137],"quantum":[138],"cost,":[139],"complexity,":[140],"estimated":[142],"delays.":[143],"The":[144],"designs":[145],"then":[147],"Altium":[150],"Designer":[151],"using":[152],"Description":[154],"Language(HDL)":[155],"verified":[157],"Xilinx":[159],"Spartan":[160],"3AN":[161],"Altera":[163],"Cyclone":[164],"I":[165],"FPGAs.":[166]},"counts_by_year":[{"year":2024,"cited_by_count":2}],"updated_date":"2026-03-10T16:38:18.471706","created_date":"2025-10-10T00:00:00"}
