{"id":"https://openalex.org/W4321192224","doi":"https://doi.org/10.1109/icce56470.2023.10043535","title":"Performance Evaluation of A New Multiplexer Design for Adaptive Logic","display_name":"Performance Evaluation of A New Multiplexer Design for Adaptive Logic","publication_year":2023,"publication_date":"2023-01-06","ids":{"openalex":"https://openalex.org/W4321192224","doi":"https://doi.org/10.1109/icce56470.2023.10043535"},"language":"en","primary_location":{"id":"doi:10.1109/icce56470.2023.10043535","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/icce56470.2023.10043535","pdf_url":null,"source":{"id":"https://openalex.org/S4363607959","display_name":"2023 IEEE International Conference on Consumer Electronics (ICCE)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE International Conference on Consumer Electronics (ICCE)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5040063993","display_name":"Karol Niewiadomski","orcid":"https://orcid.org/0000-0003-1750-8989"},"institutions":[{"id":"https://openalex.org/I167360494","display_name":"University of Wuppertal","ror":"https://ror.org/00613ak93","country_code":"DE","type":"education","lineage":["https://openalex.org/I167360494"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Karol Niewiadomski","raw_affiliation_strings":["University of Wuppertal,Chair of Automation and Computer Science,Wuppertal,Germany","Chair of Automation and Computer Science, University of Wuppertal, Wuppertal, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Wuppertal,Chair of Automation and Computer Science,Wuppertal,Germany","institution_ids":["https://openalex.org/I167360494"]},{"raw_affiliation_string":"Chair of Automation and Computer Science, University of Wuppertal, Wuppertal, Germany","institution_ids":["https://openalex.org/I167360494"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5000306618","display_name":"Dietmar Tutsch","orcid":"https://orcid.org/0009-0008-6495-5128"},"institutions":[{"id":"https://openalex.org/I167360494","display_name":"University of Wuppertal","ror":"https://ror.org/00613ak93","country_code":"DE","type":"education","lineage":["https://openalex.org/I167360494"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Dietmar Tutsch","raw_affiliation_strings":["University of Wuppertal,Chair of Automation and Computer Science,Wuppertal,Germany","Chair of Automation and Computer Science, University of Wuppertal, Wuppertal, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Wuppertal,Chair of Automation and Computer Science,Wuppertal,Germany","institution_ids":["https://openalex.org/I167360494"]},{"raw_affiliation_string":"Chair of Automation and Computer Science, University of Wuppertal, Wuppertal, Germany","institution_ids":["https://openalex.org/I167360494"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I167360494"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.00865761,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/multiplexer","display_name":"Multiplexer","score":0.959416389465332},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6880438327789307},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6429703235626221},{"id":"https://openalex.org/keywords/programmable-array-logic","display_name":"Programmable Array Logic","score":0.6172179579734802},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5895599126815796},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.548199474811554},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.49525418877601624},{"id":"https://openalex.org/keywords/macrocell-array","display_name":"Macrocell array","score":0.4829532504081726},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.46321138739585876},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.46245384216308594},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.44889241456985474},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.4327276647090912},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.41493287682533264},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3815242052078247},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.35320574045181274},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19999679923057556},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.13150089979171753},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10909602046012878},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.09605613350868225}],"concepts":[{"id":"https://openalex.org/C70970002","wikidata":"https://www.wikidata.org/wiki/Q189434","display_name":"Multiplexer","level":3,"score":0.959416389465332},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6880438327789307},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6429703235626221},{"id":"https://openalex.org/C113323844","wikidata":"https://www.wikidata.org/wiki/Q1378651","display_name":"Programmable Array Logic","level":5,"score":0.6172179579734802},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5895599126815796},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.548199474811554},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.49525418877601624},{"id":"https://openalex.org/C142278197","wikidata":"https://www.wikidata.org/wiki/Q4284934","display_name":"Macrocell array","level":5,"score":0.4829532504081726},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.46321138739585876},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.46245384216308594},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.44889241456985474},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.4327276647090912},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.41493287682533264},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3815242052078247},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.35320574045181274},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19999679923057556},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.13150089979171753},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10909602046012878},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.09605613350868225}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icce56470.2023.10043535","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/icce56470.2023.10043535","pdf_url":null,"source":{"id":"https://openalex.org/S4363607959","display_name":"2023 IEEE International Conference on Consumer Electronics (ICCE)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE International Conference on Consumer Electronics (ICCE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/14","display_name":"Life below water","score":0.8299999833106995}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1604323946","https://openalex.org/W2004018740","https://openalex.org/W2030922743","https://openalex.org/W2096810661","https://openalex.org/W2097521167","https://openalex.org/W2137663768","https://openalex.org/W2247957311","https://openalex.org/W3103339143"],"related_works":["https://openalex.org/W3013792460","https://openalex.org/W1528933814","https://openalex.org/W3117015220","https://openalex.org/W1553835358","https://openalex.org/W3105918491","https://openalex.org/W2254425074","https://openalex.org/W2034419237","https://openalex.org/W2490069675","https://openalex.org/W2102777336","https://openalex.org/W2525933112"],"abstract_inverted_index":{"Field":[0],"Programmable":[1],"Gate":[2],"Arrays":[3],"are":[4,62,85],"essential":[5],"components":[6,67],"in":[7,71],"applications,":[8],"which":[9,27],"require":[10,35],"a":[11,21,52,88],"certain":[12],"degree":[13],"of":[14,23,56],"recon-figurability.":[15],"This":[16],"feature":[17],"is":[18],"achieved":[19],"by":[20],"sea":[22],"configurable":[24],"logic":[25,50],"blocks,":[26],"realize":[28,39],"the":[29],"desired":[30],"boolean":[31],"functions.":[32],"These":[33,66],"blocks":[34],"interconnect":[36,49],"lanes":[37],"to":[38,44,87],"more":[40],"complex":[41],"functions":[42],"and":[43,77,94],"exchange":[45],"data.":[46],"In":[47,79],"consequence,":[48],"consumes":[51],"comparably":[53],"large":[54],"amount":[55],"each":[57],"FPGA":[58],"type,":[59],"where":[60],"multiplexers":[61],"an":[63],"integral":[64],"part.":[65],"can":[68],"be":[69],"realized":[70],"different":[72,75],"ways":[73],"with":[74],"advantages":[76],"drawbacks.":[78],"this":[80],"paper,":[81],"selected":[82],"multiplexer":[83,97],"designs":[84],"compared":[86],"versatile,":[89],"newly":[90],"developed,":[91],"data":[92],"retaining":[93],"power":[95],"saving":[96],"design.":[98]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}