{"id":"https://openalex.org/W2066616600","doi":"https://doi.org/10.1109/icce.2012.6161905","title":"An FPGA implementation of 3-D signal transmission system","display_name":"An FPGA implementation of 3-D signal transmission system","publication_year":2012,"publication_date":"2012-01-01","ids":{"openalex":"https://openalex.org/W2066616600","doi":"https://doi.org/10.1109/icce.2012.6161905","mag":"2066616600"},"language":"en","primary_location":{"id":"doi:10.1109/icce.2012.6161905","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icce.2012.6161905","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE International Conference on Consumer Electronics (ICCE)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100614414","display_name":"Zhen Chen","orcid":"https://orcid.org/0000-0003-2307-0047"},"institutions":[{"id":"https://openalex.org/I189442560","display_name":"Gyeongsang National University","ror":"https://ror.org/00saywf64","country_code":"KR","type":"education","lineage":["https://openalex.org/I189442560"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Zhenxing Chen","raw_affiliation_strings":["Department of Semiconductor Engineering, Gyeongsang National University, South Korea","Department of Semiconductor Engineering, Gyeongsang National University, Republic of Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Semiconductor Engineering, Gyeongsang National University, South Korea","institution_ids":["https://openalex.org/I189442560"]},{"raw_affiliation_string":"Department of Semiconductor Engineering, Gyeongsang National University, Republic of Korea","institution_ids":["https://openalex.org/I189442560"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5031346843","display_name":"Seog Geun Kang","orcid":"https://orcid.org/0000-0002-5329-3551"},"institutions":[{"id":"https://openalex.org/I189442560","display_name":"Gyeongsang National University","ror":"https://ror.org/00saywf64","country_code":"KR","type":"education","lineage":["https://openalex.org/I189442560"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Seog Geun Kang","raw_affiliation_strings":["Department of Semiconductor Engineering, Gyeongsang National University, South Korea","Department of Semiconductor Engineering, Gyeongsang National University, Republic of Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Semiconductor Engineering, Gyeongsang National University, South Korea","institution_ids":["https://openalex.org/I189442560"]},{"raw_affiliation_string":"Department of Semiconductor Engineering, Gyeongsang National University, Republic of Korea","institution_ids":["https://openalex.org/I189442560"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.2498,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.61128161,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"368","last_page":"369"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9968000054359436,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9968000054359436,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9905999898910522,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8310434818267822},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7438187599182129},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.708892822265625},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.6797959804534912},{"id":"https://openalex.org/keywords/emulation","display_name":"Emulation","score":0.6342157125473022},{"id":"https://openalex.org/keywords/encoder","display_name":"Encoder","score":0.570580005645752},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5640048980712891},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.5553744435310364},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.5078652501106262},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.49075207114219666},{"id":"https://openalex.org/keywords/transmission","display_name":"Transmission (telecommunications)","score":0.486905962228775},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4510481059551239},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.4172884225845337},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08219301700592041}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8310434818267822},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7438187599182129},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.708892822265625},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.6797959804534912},{"id":"https://openalex.org/C149810388","wikidata":"https://www.wikidata.org/wiki/Q5374873","display_name":"Emulation","level":2,"score":0.6342157125473022},{"id":"https://openalex.org/C118505674","wikidata":"https://www.wikidata.org/wiki/Q42586063","display_name":"Encoder","level":2,"score":0.570580005645752},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5640048980712891},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.5553744435310364},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.5078652501106262},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.49075207114219666},{"id":"https://openalex.org/C761482","wikidata":"https://www.wikidata.org/wiki/Q118093","display_name":"Transmission (telecommunications)","level":2,"score":0.486905962228775},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4510481059551239},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.4172884225845337},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08219301700592041},{"id":"https://openalex.org/C50522688","wikidata":"https://www.wikidata.org/wiki/Q189833","display_name":"Economic growth","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icce.2012.6161905","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icce.2012.6161905","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE International Conference on Consumer Electronics (ICCE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W2066630987","https://openalex.org/W2099178466","https://openalex.org/W2147670156","https://openalex.org/W2152953137","https://openalex.org/W2153302213","https://openalex.org/W2159167842","https://openalex.org/W2798333393"],"related_works":["https://openalex.org/W2110818533","https://openalex.org/W1917852300","https://openalex.org/W2111408175","https://openalex.org/W2384838054","https://openalex.org/W2139058049","https://openalex.org/W2376018793","https://openalex.org/W2548456620","https://openalex.org/W2911649771","https://openalex.org/W2148697719","https://openalex.org/W2290175651"],"abstract_inverted_index":{"A":[0],"3-dimensinal":[1],"(3-D)":[2],"signal":[3,23],"transmission":[4],"system":[5,77,97],"is":[6,92],"implemented":[7,50,96],"on":[8,70],"field":[9],"programmable":[10],"gate":[11],"array":[12],"(FPGA)":[13],"in":[14],"this":[15],"paper.":[16],"We":[17],"exploit":[18],"3-D":[19],"8-ary":[20],"and":[21,30,47,63],"32-ary":[22],"constellations":[24],"to":[25,35],"map":[26],"input":[27],"binary":[28],"data,":[29],"Gram-Schmidt":[31],"orthogonalization":[32],"procedure":[33],"(GSOP)":[34],"generate":[36],"transmitted":[37],"signals.":[38],"The":[39,59],"prototypes":[40],"of":[41,53],"function":[42],"modules":[43,60],"such":[44],"as":[45,86],"encoder":[46],"demapper":[48],"are":[49,61],"by":[51],"means":[52],"Verilog":[54],"hardware":[55],"description":[56],"language":[57],"(VHDL).":[58],"synthesized":[62],"emulated":[64],"using":[65],"FPGA":[66],"tools.":[67],"Emulation":[68],"based":[69],"the":[71,76,80,95],"fixed-point":[72],"format":[73],"demonstrates":[74],"that":[75,94],"has":[78],"almost":[79],"same":[81],"symbol":[82],"error":[83],"rate":[84],"(SER)":[85],"a":[87],"software":[88],"test-bed.":[89],"Hence,":[90],"it":[91],"considered":[93],"operates":[98],"correctly.":[99]},"counts_by_year":[{"year":2015,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}