{"id":"https://openalex.org/W3006650799","doi":"https://doi.org/10.1109/icce-tw46550.2019.8991975","title":"A study on Inter-Board Data Transmission of FPGA Cluster","display_name":"A study on Inter-Board Data Transmission of FPGA Cluster","publication_year":2019,"publication_date":"2019-05-01","ids":{"openalex":"https://openalex.org/W3006650799","doi":"https://doi.org/10.1109/icce-tw46550.2019.8991975","mag":"3006650799"},"language":"en","primary_location":{"id":"doi:10.1109/icce-tw46550.2019.8991975","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icce-tw46550.2019.8991975","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5031577245","display_name":"Naohisa Fukase","orcid":null},"institutions":[{"id":"https://openalex.org/I197425175","display_name":"Shonan Institute of Technology","ror":"https://ror.org/01bawqf59","country_code":"JP","type":"education","lineage":["https://openalex.org/I197425175"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Naohisa Fukase","raw_affiliation_strings":["Shonan Institute of Technology"],"affiliations":[{"raw_affiliation_string":"Shonan Institute of Technology","institution_ids":["https://openalex.org/I197425175"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082362242","display_name":"Hironobu Handa","orcid":"https://orcid.org/0009-0004-4989-7063"},"institutions":[{"id":"https://openalex.org/I197425175","display_name":"Shonan Institute of Technology","ror":"https://ror.org/01bawqf59","country_code":"JP","type":"education","lineage":["https://openalex.org/I197425175"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Hironobu Handa","raw_affiliation_strings":["Shonan Institute of Technology"],"affiliations":[{"raw_affiliation_string":"Shonan Institute of Technology","institution_ids":["https://openalex.org/I197425175"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067887693","display_name":"Akihisa Furuichi","orcid":null},"institutions":[{"id":"https://openalex.org/I197425175","display_name":"Shonan Institute of Technology","ror":"https://ror.org/01bawqf59","country_code":"JP","type":"education","lineage":["https://openalex.org/I197425175"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Akihisa Furuichi","raw_affiliation_strings":["Shonan Institute of Technology"],"affiliations":[{"raw_affiliation_string":"Shonan Institute of Technology","institution_ids":["https://openalex.org/I197425175"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5070862348","display_name":"Yasuyuki Miura","orcid":null},"institutions":[{"id":"https://openalex.org/I197425175","display_name":"Shonan Institute of Technology","ror":"https://ror.org/01bawqf59","country_code":"JP","type":"education","lineage":["https://openalex.org/I197425175"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Yasuyuki Miura","raw_affiliation_strings":["Shonan Institute of Technology"],"affiliations":[{"raw_affiliation_string":"Shonan Institute of Technology","institution_ids":["https://openalex.org/I197425175"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5031577245"],"corresponding_institution_ids":["https://openalex.org/I197425175"],"apc_list":null,"apc_paid":null,"fwci":0.2408,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.54148187,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9659000039100647,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9659000039100647,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9577999711036682,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9532999992370605,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8941584825515747},{"id":"https://openalex.org/keywords/router","display_name":"Router","score":0.8286774158477783},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.8117865324020386},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7234214544296265},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6087828278541565},{"id":"https://openalex.org/keywords/data-transmission","display_name":"Data transmission","score":0.4565410912036896},{"id":"https://openalex.org/keywords/extensibility","display_name":"Extensibility","score":0.4563901424407959},{"id":"https://openalex.org/keywords/cluster","display_name":"Cluster (spacecraft)","score":0.45286011695861816},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.44433778524398804},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3403847813606262},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.24504777789115906},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.13202202320098877}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8941584825515747},{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.8286774158477783},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.8117865324020386},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7234214544296265},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6087828278541565},{"id":"https://openalex.org/C557945733","wikidata":"https://www.wikidata.org/wiki/Q389772","display_name":"Data transmission","level":2,"score":0.4565410912036896},{"id":"https://openalex.org/C32833848","wikidata":"https://www.wikidata.org/wiki/Q4115054","display_name":"Extensibility","level":2,"score":0.4563901424407959},{"id":"https://openalex.org/C164866538","wikidata":"https://www.wikidata.org/wiki/Q367351","display_name":"Cluster (spacecraft)","level":2,"score":0.45286011695861816},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.44433778524398804},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3403847813606262},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.24504777789115906},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.13202202320098877}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icce-tw46550.2019.8991975","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icce-tw46550.2019.8991975","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W1948607442","https://openalex.org/W3004004161","https://openalex.org/W2044615423","https://openalex.org/W4247766898","https://openalex.org/W4244765761","https://openalex.org/W2361584951","https://openalex.org/W1601859592","https://openalex.org/W2375477056","https://openalex.org/W2367070068","https://openalex.org/W2357701679"],"abstract_inverted_index":{"In":[0,63],"recent":[1],"years,":[2],"using":[3],"field-programmable":[4],"gate":[5],"arrays":[6],"(FPGAs)":[7],"to":[8,56,91,105,115,134],"improve":[9],"computer":[10],"performance":[11],"has":[12,54],"attracted":[13],"attention,":[14],"and":[15,36,52,61,99,125],"configuration":[16],"methods":[17,80],"such":[18],"as":[19],"FPGA":[20,43,73],"clusters,":[21],"which":[22],"are":[23,75],"one":[24],"of":[25,41,65,108,138],"the":[26,42,85,106,135],"ways":[27],"they":[28],"can":[29],"be":[30],"implemented,":[31],"have":[32,47,81],"been":[33],"extensively":[34],"researched":[35],"used.":[37],"The":[38],"router":[39,118],"circuit":[40,119],"cluster":[44],"does":[45],"not":[46],"a":[48,117],"specific":[49],"production":[50],"method,":[51],"it":[53,103],"led":[55],"an":[57,93,122,127],"increase":[58],"in":[59,84],"research":[60],"development.":[62],"view":[64],"these":[66],"circumstances,":[67],"general":[68],"purpose":[69],"connection":[70],"networks":[71],"for":[72,110,120],"clusters":[74],"being":[76],"studied.":[77],"However,":[78],"many":[79],"unique":[82],"specifications":[83,107],"interconnection":[86,94,123],"network.":[87],"Therefore,":[88],"we":[89],"aim":[90,114],"develop":[92],"network":[95,124],"with":[96],"high":[97],"versatility":[98],"extensibility":[100],"by":[101],"making":[102],"according":[104],"Qsys":[109],"Intel\u00ae":[111],"FPGA.":[112],"We":[113],"prepare":[116],"constructing":[121],"conducted":[126],"operation":[128],"test.":[129],"It":[130],"operated":[131],"normally":[132],"up":[133],"operating":[136],"frequency":[137],"150":[139],"MHz.":[140]},"counts_by_year":[{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
