{"id":"https://openalex.org/W1574514933","doi":"https://doi.org/10.1109/icce-tw.2015.7216842","title":"Efficient memory management scheme for pipelined shared-memory FFT processors","display_name":"Efficient memory management scheme for pipelined shared-memory FFT processors","publication_year":2015,"publication_date":"2015-06-01","ids":{"openalex":"https://openalex.org/W1574514933","doi":"https://doi.org/10.1109/icce-tw.2015.7216842","mag":"1574514933"},"language":"en","primary_location":{"id":"doi:10.1109/icce-tw.2015.7216842","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icce-tw.2015.7216842","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Conference on Consumer Electronics - Taiwan","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5029828204","display_name":"Hsin-Fu Luo","orcid":null},"institutions":[{"id":"https://openalex.org/I91807558","display_name":"National Cheng Kung University","ror":"https://ror.org/01b8kcc49","country_code":"TW","type":"education","lineage":["https://openalex.org/I91807558"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Hsin-Fu Luo","raw_affiliation_strings":["Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan","Department of Electrical Engineering, National Cheng Kung University, Tainan (Taiwan)"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan","institution_ids":["https://openalex.org/I91807558"]},{"raw_affiliation_string":"Department of Electrical Engineering, National Cheng Kung University, Tainan (Taiwan)","institution_ids":["https://openalex.org/I91807558"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5053167526","display_name":"Ming\u2010Der Shieh","orcid":"https://orcid.org/0000-0002-7361-1860"},"institutions":[{"id":"https://openalex.org/I91807558","display_name":"National Cheng Kung University","ror":"https://ror.org/01b8kcc49","country_code":"TW","type":"education","lineage":["https://openalex.org/I91807558"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Ming-Der Shieh","raw_affiliation_strings":["Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan","Department of Electrical Engineering, National Cheng Kung University, Tainan (Taiwan)"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan","institution_ids":["https://openalex.org/I91807558"]},{"raw_affiliation_string":"Department of Electrical Engineering, National Cheng Kung University, Tainan (Taiwan)","institution_ids":["https://openalex.org/I91807558"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5029828204"],"corresponding_institution_ids":["https://openalex.org/I91807558"],"apc_list":null,"apc_paid":null,"fwci":0.2872,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.52705224,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"2","issue":null,"first_page":"178","last_page":"179"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9948999881744385,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9948999881744385,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9876999855041504,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9550999999046326,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8292403221130371},{"id":"https://openalex.org/keywords/fast-fourier-transform","display_name":"Fast Fourier transform","score":0.7086102962493896},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6589251756668091},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.5389806032180786},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.5160210132598877},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.49268919229507446},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.47266945242881775},{"id":"https://openalex.org/keywords/flat-memory-model","display_name":"Flat memory model","score":0.4497048556804657},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.43530669808387756},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.30198365449905396},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.24068361520767212},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.23357316851615906}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8292403221130371},{"id":"https://openalex.org/C75172450","wikidata":"https://www.wikidata.org/wiki/Q623950","display_name":"Fast Fourier transform","level":2,"score":0.7086102962493896},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6589251756668091},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.5389806032180786},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.5160210132598877},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.49268919229507446},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.47266945242881775},{"id":"https://openalex.org/C57863822","wikidata":"https://www.wikidata.org/wiki/Q905488","display_name":"Flat memory model","level":4,"score":0.4497048556804657},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.43530669808387756},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.30198365449905396},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.24068361520767212},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.23357316851615906},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icce-tw.2015.7216842","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icce-tw.2015.7216842","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Conference on Consumer Electronics - Taiwan","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8500000238418579,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1976676268","https://openalex.org/W2103819235","https://openalex.org/W2109070029","https://openalex.org/W2135502072","https://openalex.org/W2535552192","https://openalex.org/W6675256727"],"related_works":["https://openalex.org/W4312264564","https://openalex.org/W4248614727","https://openalex.org/W2296275612","https://openalex.org/W2526783553","https://openalex.org/W120214571","https://openalex.org/W1975698617","https://openalex.org/W4281569059","https://openalex.org/W2561005478","https://openalex.org/W2143690511","https://openalex.org/W2036525499"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"an":[3],"efficient":[4],"memory":[5,50,74],"management":[6],"scheme":[7,27],"for":[8,34],"pipelined":[9,43,67],"shared-memory":[10,44,68],"architectures":[11,58],"of":[12,42,78],"the":[13,36,79],"fast":[14],"Fourier":[15],"transform":[16],"(FFT).":[17],"A":[18],"multi-path":[19],"delay":[20],"commutator":[21],"(MDC)":[22],"with":[23],"a":[24,48],"data":[25],"relocation":[26],"is":[28,59],"developed":[29],"to":[30],"merge":[31],"multiple":[32],"banks":[33],"lowering":[35],"area":[37,80],"requirement":[38,81],"and":[39,82],"power":[40,83],"dissipation":[41],"FFT":[45,69],"architectures.":[46],"Moreover,":[47],"generalized":[49],"addressing":[51],"algorithm":[52],"that":[53],"can":[54],"support":[55],"mixed-radix":[56],"MDC":[57],"also":[60],"proposed.":[61],"The":[62],"presented":[63],"architecture":[64],"outperforms":[65],"conventional":[66],"designs,":[70],"which":[71],"employ":[72],"multi-bank":[73],"structures,":[75],"in":[76],"terms":[77],"consumption.":[84]},"counts_by_year":[{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
