{"id":"https://openalex.org/W3109611933","doi":"https://doi.org/10.1109/icce-taiwan49838.2020.9258225","title":"A Baseband All-Digital Clock and Data Recovery Circuit with A Limited Range Binary Search FSM","display_name":"A Baseband All-Digital Clock and Data Recovery Circuit with A Limited Range Binary Search FSM","publication_year":2020,"publication_date":"2020-09-28","ids":{"openalex":"https://openalex.org/W3109611933","doi":"https://doi.org/10.1109/icce-taiwan49838.2020.9258225","mag":"3109611933"},"language":"en","primary_location":{"id":"doi:10.1109/icce-taiwan49838.2020.9258225","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icce-taiwan49838.2020.9258225","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-Taiwan)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5086094275","display_name":"Jia-Ken Li","orcid":null},"institutions":[{"id":"https://openalex.org/I99908691","display_name":"Yuan Ze University","ror":"https://ror.org/01fv1ds98","country_code":"TW","type":"education","lineage":["https://openalex.org/I99908691"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Jia-Ken Li","raw_affiliation_strings":["Yuan Ze university, Chung-Li, Taiwan"],"affiliations":[{"raw_affiliation_string":"Yuan Ze university, Chung-Li, Taiwan","institution_ids":["https://openalex.org/I99908691"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112229848","display_name":"Hung-Wen Lin","orcid":null},"institutions":[{"id":"https://openalex.org/I99908691","display_name":"Yuan Ze University","ror":"https://ror.org/01fv1ds98","country_code":"TW","type":"education","lineage":["https://openalex.org/I99908691"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Hung-Wen Lin","raw_affiliation_strings":["Yuan Ze university, Chung-Li, Taiwan"],"affiliations":[{"raw_affiliation_string":"Yuan Ze university, Chung-Li, Taiwan","institution_ids":["https://openalex.org/I99908691"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5086094275"],"corresponding_institution_ids":["https://openalex.org/I99908691"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.12198768,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-generator","display_name":"Clock generator","score":0.7623886466026306},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.731669545173645},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5892554521560669},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5235297679901123},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.486198365688324},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.4782335162162781},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.46182164549827576},{"id":"https://openalex.org/keywords/baseband","display_name":"Baseband","score":0.4610331356525421},{"id":"https://openalex.org/keywords/data-recovery","display_name":"Data recovery","score":0.4589385390281677},{"id":"https://openalex.org/keywords/digital-clock","display_name":"Digital clock","score":0.4556669294834137},{"id":"https://openalex.org/keywords/phase-detector","display_name":"Phase detector","score":0.44650131464004517},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.4332757592201233},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.41965004801750183},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.3217694163322449},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3176097869873047},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.2820061445236206},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.20126166939735413},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.184693843126297},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.0972844660282135}],"concepts":[{"id":"https://openalex.org/C2778023540","wikidata":"https://www.wikidata.org/wiki/Q2164847","display_name":"Clock generator","level":4,"score":0.7623886466026306},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.731669545173645},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5892554521560669},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5235297679901123},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.486198365688324},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.4782335162162781},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.46182164549827576},{"id":"https://openalex.org/C65165936","wikidata":"https://www.wikidata.org/wiki/Q575784","display_name":"Baseband","level":3,"score":0.4610331356525421},{"id":"https://openalex.org/C529754248","wikidata":"https://www.wikidata.org/wiki/Q1054772","display_name":"Data recovery","level":2,"score":0.4589385390281677},{"id":"https://openalex.org/C2778426721","wikidata":"https://www.wikidata.org/wiki/Q1225105","display_name":"Digital clock","level":3,"score":0.4556669294834137},{"id":"https://openalex.org/C110086884","wikidata":"https://www.wikidata.org/wiki/Q2085341","display_name":"Phase detector","level":3,"score":0.44650131464004517},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.4332757592201233},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.41965004801750183},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.3217694163322449},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3176097869873047},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.2820061445236206},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.20126166939735413},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.184693843126297},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0972844660282135}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icce-taiwan49838.2020.9258225","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icce-taiwan49838.2020.9258225","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-Taiwan)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.5600000023841858}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2000345125","https://openalex.org/W2068876400","https://openalex.org/W2109307238","https://openalex.org/W2112543413","https://openalex.org/W2114799023"],"related_works":["https://openalex.org/W2124909075","https://openalex.org/W1607003253","https://openalex.org/W2167127845","https://openalex.org/W127191621","https://openalex.org/W2130365397","https://openalex.org/W3215045041","https://openalex.org/W2151516060","https://openalex.org/W2003234253","https://openalex.org/W3013924136","https://openalex.org/W2127923272"],"abstract_inverted_index":{"This":[0],"paper":[1],"proposes":[2],"an":[3,39],"all-digital-phase-locked-loop":[4],"(ADPLL)-based":[5],"clock-and-data-recovery":[6],"circuit":[7,12],"(CDR)":[8],"for":[9,16],"the":[10,27,51,91,95,111],"baseband":[11],"system.":[13],"To":[14,34],"apply":[15],"different":[17,31],"data-rate,":[18],"a":[19,43,104],"programmable":[20],"digital-control-clock-phase-generator":[21],"(DCPG)":[22],"was":[23,48,60],"designed":[24],"to":[25,100],"generate":[26],"recovery":[28,112],"clock":[29,84,113],"with":[30,117],"phase":[32,41],"resolution.":[33],"perform":[35],"binary":[36,45],"search":[37,46],"at":[38],"arbitrary":[40],"number,":[42],"limited-range":[44],"flow":[47],"added":[49],"into":[50],"phase-frequency-control":[52],"finite":[53],"state":[54],"machine":[55],"(PFCFSM).":[56],"The":[57],"proposed":[58],"CDR":[59],"verified":[61],"in":[62],"0.18":[63],"\u03bcm":[64,70,72],"CMOS":[65],"process":[66],"and":[67,85,102,114,119],"occupied":[68],"200":[69],"\u00d7225":[71],"of":[73,78,82,87,107,121],"core":[74],"area.":[75],"With":[76],"1V":[77],"supply":[79],"voltage,":[80],"200MHz":[81],"reference":[83],"500ppm":[86],"data":[88,96,115],"frequency":[89],"offset,":[90],"chip":[92],"results":[93],"shows":[94],"rate":[97],"from":[98],"1Mbps":[99],"5.5Mbps":[101],"consumes":[103],"total":[105],"power":[106],"0.22mW.":[108],"At":[109],"5.5Mbps,":[110],"are":[116],"0.025UI":[118],"0.0475UI":[120],"timing":[122],"jitter,":[123],"respectively.":[124]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
