{"id":"https://openalex.org/W2555398284","doi":"https://doi.org/10.1109/iccd.2016.7753303","title":"AIBA: An Automated Intra-cycle Behavioral Analysis for SystemC-based design exploration","display_name":"AIBA: An Automated Intra-cycle Behavioral Analysis for SystemC-based design exploration","publication_year":2016,"publication_date":"2016-10-01","ids":{"openalex":"https://openalex.org/W2555398284","doi":"https://doi.org/10.1109/iccd.2016.7753303","mag":"2555398284"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.2016.7753303","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2016.7753303","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE 34th International Conference on Computer Design (ICCD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5086748944","display_name":"Mehran Goli","orcid":"https://orcid.org/0000-0002-1256-4140"},"institutions":[{"id":"https://openalex.org/I180437899","display_name":"University of Bremen","ror":"https://ror.org/04ers2y35","country_code":"DE","type":"education","lineage":["https://openalex.org/I180437899"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Mehran Goli","raw_affiliation_strings":["Institute of Computer Science, University of Bremen, Bremen, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Computer Science, University of Bremen, Bremen, Germany","institution_ids":["https://openalex.org/I180437899"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074452368","display_name":"Jannis Stoppe","orcid":"https://orcid.org/0000-0003-2952-3422"},"institutions":[{"id":"https://openalex.org/I180437899","display_name":"University of Bremen","ror":"https://ror.org/04ers2y35","country_code":"DE","type":"education","lineage":["https://openalex.org/I180437899"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Jannis Stoppe","raw_affiliation_strings":["Universitat Bremen, Bremen, Bremen, DE"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Universitat Bremen, Bremen, Bremen, DE","institution_ids":["https://openalex.org/I180437899"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5071742136","display_name":"Rolf Drechsler","orcid":"https://orcid.org/0000-0002-9872-1740"},"institutions":[{"id":"https://openalex.org/I180437899","display_name":"University of Bremen","ror":"https://ror.org/04ers2y35","country_code":"DE","type":"education","lineage":["https://openalex.org/I180437899"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Rolf Drechsler","raw_affiliation_strings":["Institute of Computer Science, University of Bremen, Bremen, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Computer Science, University of Bremen, Bremen, Germany","institution_ids":["https://openalex.org/I180437899"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I180437899"],"apc_list":null,"apc_paid":null,"fwci":1.9223,"has_fulltext":false,"cited_by_count":20,"citation_normalized_percentile":{"value":0.85965232,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.8473315238952637},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7870772480964661},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5741788744926453},{"id":"https://openalex.org/keywords/debugger","display_name":"Debugger","score":0.5702527761459351},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5680779218673706},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4856239855289459},{"id":"https://openalex.org/keywords/behavioral-modeling","display_name":"Behavioral modeling","score":0.4663236737251282},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.4451286196708679},{"id":"https://openalex.org/keywords/design-methods","display_name":"Design methods","score":0.43881502747535706},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.41865071654319763},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.4110143780708313},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3594517707824707},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.2201264500617981},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.12048590183258057},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.11471971869468689},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10043114423751831},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.08693808317184448}],"concepts":[{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.8473315238952637},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7870772480964661},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5741788744926453},{"id":"https://openalex.org/C2778485113","wikidata":"https://www.wikidata.org/wiki/Q193231","display_name":"Debugger","level":3,"score":0.5702527761459351},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5680779218673706},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4856239855289459},{"id":"https://openalex.org/C78639753","wikidata":"https://www.wikidata.org/wiki/Q3318160","display_name":"Behavioral modeling","level":2,"score":0.4663236737251282},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.4451286196708679},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.43881502747535706},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.41865071654319763},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.4110143780708313},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3594517707824707},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.2201264500617981},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.12048590183258057},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.11471971869468689},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10043114423751831},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.08693808317184448},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccd.2016.7753303","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2016.7753303","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE 34th International Conference on Computer Design (ICCD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.5699999928474426,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W54729521","https://openalex.org/W141357097","https://openalex.org/W161175043","https://openalex.org/W1551628827","https://openalex.org/W1556078275","https://openalex.org/W1587166803","https://openalex.org/W1592895353","https://openalex.org/W1607765501","https://openalex.org/W2007892863","https://openalex.org/W2043132803","https://openalex.org/W2060349165","https://openalex.org/W2083618878","https://openalex.org/W2108762938","https://openalex.org/W2125316325","https://openalex.org/W2137605233","https://openalex.org/W2545252583","https://openalex.org/W3149523651","https://openalex.org/W4248570280","https://openalex.org/W4254476029"],"related_works":["https://openalex.org/W1603163876","https://openalex.org/W2133642747","https://openalex.org/W2035070505","https://openalex.org/W2359630088","https://openalex.org/W47369351","https://openalex.org/W2028583644","https://openalex.org/W2166219277","https://openalex.org/W2102117846","https://openalex.org/W2104872320","https://openalex.org/W2139653418"],"abstract_inverted_index":{"In":[0,91],"order":[1],"to":[2,36,54,108,137],"overcome":[3],"the":[4,14,49,64,71,82,96,105,133,146,149],"ever":[5],"increasing":[6],"complexity":[7],"of":[8,23,48,73,84,119,148],"digital":[9],"circuits,":[10],"system":[11,86],"design":[12,37],"at":[13],"Electronic":[15],"System":[16],"Level":[17],"(ESL)":[18],"has":[19],"become":[20],"an":[21],"area":[22],"active":[24],"research.":[25],"SystemC":[26,130],"provides":[27],"designers":[28,62,77],"with":[29,78],"a":[30,42,110],"readily-available":[31],"ESL":[32,120],"framework,":[33],"allowing":[34,128],"them":[35],"mixed":[38],"hardware/software":[39],"systems":[40],"using":[41],"standardized":[43],"C++":[44],"library.":[45],"The":[46,122],"analysis":[47,112],"resulting":[50],"designs":[51,131],"is":[52,125],"crucial":[53],"e.g.":[55],"apply":[56],"additional":[57],"validation":[58],"steps":[59],"or":[60],"assist":[61],"during":[63],"development":[65],"process.":[66],"Existing":[67],"approaches":[68],"focus":[69],"on":[70],"extraction":[72],"static":[74],"information,":[75],"providing":[76],"models":[79],"that":[80,113],"describe":[81],"structure":[83],"their":[85],"but":[87],"not":[88],"its":[89],"behavior.":[90],"this":[92],"paper,":[93],"we":[94],"introduce":[95],"Automated":[97],"Intra-cycle":[98],"Behavioral":[99],"Analysis":[100],"tool,":[101],"AIBA.":[102],"AIBA":[103],"utilizes":[104],"GNU":[106],"debugger":[107],"execute":[109],"two-step":[111],"retrieves":[114],"behavioral":[115],"and":[116,132],"architectural":[117],"information":[118],"designs.":[121],"proposed":[123],"method":[124],"completely":[126],"non-intrusive,":[127],"both":[129],"standard":[134],"tool":[135],"flow":[136],"be":[138],"used":[139],"without":[140],"any":[141],"modification.":[142],"Case":[143],"studies":[144],"confirm":[145],"benefits":[147],"approach.":[150]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":5},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":2}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}