{"id":"https://openalex.org/W2554588902","doi":"https://doi.org/10.1109/iccd.2016.7753295","title":"Exploiting cache coherence for effective on-the-fly data tracing in multicores","display_name":"Exploiting cache coherence for effective on-the-fly data tracing in multicores","publication_year":2016,"publication_date":"2016-10-01","ids":{"openalex":"https://openalex.org/W2554588902","doi":"https://doi.org/10.1109/iccd.2016.7753295","mag":"2554588902"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.2016.7753295","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2016.7753295","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE 34th International Conference on Computer Design (ICCD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5063574003","display_name":"Mounika Ponugoti","orcid":null},"institutions":[{"id":"https://openalex.org/I82495205","display_name":"University of Alabama in Huntsville","ror":"https://ror.org/02zsxwr40","country_code":"US","type":"education","lineage":["https://openalex.org/I82495205"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mounika Ponugoti","raw_affiliation_strings":["Department of Electrical and Computer Engineering, The University of Alabama Huntsville, Huntsville, AL, U.S.A"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, The University of Alabama Huntsville, Huntsville, AL, U.S.A","institution_ids":["https://openalex.org/I82495205"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5083066313","display_name":"Aleksandar Milenkovi\u0107","orcid":"https://orcid.org/0000-0002-9359-4594"},"institutions":[{"id":"https://openalex.org/I82495205","display_name":"University of Alabama in Huntsville","ror":"https://ror.org/02zsxwr40","country_code":"US","type":"education","lineage":["https://openalex.org/I82495205"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Aleksandar Milenkovic","raw_affiliation_strings":["Department of Electrical and Computer Engineering, The University of Alabama Huntsville, Huntsville, AL, U.S.A"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, The University of Alabama Huntsville, Huntsville, AL, U.S.A","institution_ids":["https://openalex.org/I82495205"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I82495205"],"apc_list":null,"apc_paid":null,"fwci":0.3204,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.60316738,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"1","issue":null,"first_page":"312","last_page":"319"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8575480580329895},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.5858218669891357},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5677411556243896},{"id":"https://openalex.org/keywords/tracing","display_name":"Tracing","score":0.5492177605628967},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.465109646320343},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.4456602931022644},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.44436320662498474},{"id":"https://openalex.org/keywords/cache-coherence","display_name":"Cache coherence","score":0.412770539522171},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.3717464804649353},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3478671908378601},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.33854061365127563},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.30890053510665894}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8575480580329895},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.5858218669891357},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5677411556243896},{"id":"https://openalex.org/C138673069","wikidata":"https://www.wikidata.org/wiki/Q322229","display_name":"Tracing","level":2,"score":0.5492177605628967},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.465109646320343},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.4456602931022644},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.44436320662498474},{"id":"https://openalex.org/C141917322","wikidata":"https://www.wikidata.org/wiki/Q1025017","display_name":"Cache coherence","level":5,"score":0.412770539522171},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.3717464804649353},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3478671908378601},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.33854061365127563},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.30890053510665894}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccd.2016.7753295","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2016.7753295","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE 34th International Conference on Computer Design (ICCD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1855846942","https://openalex.org/W2084278425","https://openalex.org/W2090830330","https://openalex.org/W2098816443","https://openalex.org/W2103742924","https://openalex.org/W2115936097","https://openalex.org/W2121990550","https://openalex.org/W2145021036","https://openalex.org/W4238549726"],"related_works":["https://openalex.org/W2290179447","https://openalex.org/W2337418885","https://openalex.org/W4207012101","https://openalex.org/W2123859627","https://openalex.org/W3139889547","https://openalex.org/W2057019356","https://openalex.org/W1993010599","https://openalex.org/W2061075966","https://openalex.org/W2147122795","https://openalex.org/W3147501184"],"abstract_inverted_index":{"Software":[0],"testing":[1],"and":[2,18,23,25,40,56,77,101,169,214],"debugging":[3],"of":[4,49,65,90,110,119,143,152,165,172],"modern":[5],"embedded":[6],"computer":[7],"systems":[8],"become":[9],"increasingly":[10],"a":[11,62,71,87,91,131,163],"challenging":[12],"task":[13],"due":[14],"to":[15,106,116,123,191,208,217],"growing":[16,63],"hardware":[17,144],"software":[19,31,125],"complexity,":[20],"increased":[21],"integration":[22],"miniaturization,":[24],"ever":[26],"tightening":[27],"time-to-market.":[28],"To":[29],"find":[30],"bugs":[32],"faster,":[33],"developers":[34],"often":[35],"rely":[36],"on":[37,130,199],"on-chip":[38],"trace":[39,111,133,159,186],"debug":[41],"resources.":[42],"However,":[43],"these":[44],"resources":[45],"offer":[46],"limited":[47],"visibility":[48],"the":[50,53,108,120,124,141,150,153,158,166,170,179,184,192,203],"system,":[51],"increase":[52],"system":[54],"cost,":[55],"do":[57],"not":[58],"scale":[59],"well":[60],"with":[61],"number":[64,109,171],"processor":[66,173],"cores.":[67,174,222],"This":[68],"paper":[69],"introduces":[70],"new":[72],"hardware/software":[73],"mechanism":[74,97,128,181],"for":[75,211,220],"capturing":[76],"filtering":[78],"load":[79,194],"data":[80,99,136,195,200],"value":[81,196],"traces":[82],"in":[83],"multicores":[84],"that":[85,113,178],"enables":[86],"complete":[88],"reconstruction":[89],"parallel":[92],"program":[93],"execution.":[94],"The":[95,127,175],"proposed":[96,154,180],"exploits":[98],"caches":[100],"cache":[102,137,167,201],"coherence":[103],"protocol":[104],"states":[105],"minimize":[107],"events":[112],"are":[114],"necessary":[115],"stream":[117],"out":[118],"target":[121],"platform":[122],"debugger.":[126],"relies":[129],"single":[132,212],"bit":[134],"per":[135],"block,":[138],"thus":[139],"minimizing":[140],"cost":[142],"implementation.":[145],"Our":[146],"experimental":[147],"evaluation":[148],"explores":[149],"effectiveness":[151],"technique":[155],"by":[156],"measuring":[157],"port":[160,187],"bandwidth":[161,188],"as":[162],"function":[164],"size":[168],"results":[176],"show":[177],"significantly":[182],"reduces":[183],"required":[185],"when":[189],"compared":[190],"Nexus-like":[193],"tracing.":[197],"Depending":[198],"size,":[202],"improvements":[204],"range":[205],"from":[206,215],"9.9":[207],"23.5":[209],"times":[210,219],"cores":[213],"18.6":[216],"37.3":[218],"octa":[221]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":1}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}
