{"id":"https://openalex.org/W2553117580","doi":"https://doi.org/10.1109/iccd.2016.7753270","title":"Dynamic prefetcher reconfiguration for diverse memory architectures","display_name":"Dynamic prefetcher reconfiguration for diverse memory architectures","publication_year":2016,"publication_date":"2016-10-01","ids":{"openalex":"https://openalex.org/W2553117580","doi":"https://doi.org/10.1109/iccd.2016.7753270","mag":"2553117580"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.2016.7753270","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2016.7753270","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE 34th International Conference on Computer Design (ICCD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100626268","display_name":"Junghoon Lee","orcid":"https://orcid.org/0000-0001-5595-191X"},"institutions":[{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Junghoon Lee","raw_affiliation_strings":["Samsung Advanced Institute of Technology"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Samsung Advanced Institute of Technology","institution_ids":["https://openalex.org/I2250650973"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100379045","display_name":"Taehoon Kim","orcid":"https://orcid.org/0000-0003-1819-968X"},"institutions":[{"id":"https://openalex.org/I157485424","display_name":"Korea Advanced Institute of Science and Technology","ror":"https://ror.org/05apxxy63","country_code":"KR","type":"education","lineage":["https://openalex.org/I157485424"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Taehoon Kim","raw_affiliation_strings":["KAIST, School of Computing"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"KAIST, School of Computing","institution_ids":["https://openalex.org/I157485424"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5047149607","display_name":"Jaehyuk Huh","orcid":"https://orcid.org/0000-0002-1742-047X"},"institutions":[{"id":"https://openalex.org/I157485424","display_name":"Korea Advanced Institute of Science and Technology","ror":"https://ror.org/05apxxy63","country_code":"KR","type":"education","lineage":["https://openalex.org/I157485424"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Jaehyuk Huh","raw_affiliation_strings":["KAIST, School of Computing"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"KAIST, School of Computing","institution_ids":["https://openalex.org/I157485424"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.13175614,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"125","last_page":"132"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8385557532310486},{"id":"https://openalex.org/keywords/instruction-prefetch","display_name":"Instruction prefetch","score":0.8152047395706177},{"id":"https://openalex.org/keywords/flat-memory-model","display_name":"Flat memory model","score":0.7245895862579346},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.648119330406189},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.6344605684280396},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.5481014251708984},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.5063349008560181},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.48856720328330994},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.45969051122665405},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.45705437660217285},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.4555242955684662},{"id":"https://openalex.org/keywords/non-uniform-memory-access","display_name":"Non-uniform memory access","score":0.4533589780330658},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.45059096813201904},{"id":"https://openalex.org/keywords/memory-map","display_name":"Memory map","score":0.4368826746940613},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4276025891304016},{"id":"https://openalex.org/keywords/physical-address","display_name":"Physical address","score":0.4203537404537201},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3508259057998657},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.26082372665405273},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.23875969648361206}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8385557532310486},{"id":"https://openalex.org/C133588205","wikidata":"https://www.wikidata.org/wiki/Q28455645","display_name":"Instruction prefetch","level":3,"score":0.8152047395706177},{"id":"https://openalex.org/C57863822","wikidata":"https://www.wikidata.org/wiki/Q905488","display_name":"Flat memory model","level":4,"score":0.7245895862579346},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.648119330406189},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.6344605684280396},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.5481014251708984},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.5063349008560181},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.48856720328330994},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.45969051122665405},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.45705437660217285},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.4555242955684662},{"id":"https://openalex.org/C133371097","wikidata":"https://www.wikidata.org/wiki/Q868014","display_name":"Non-uniform memory access","level":5,"score":0.4533589780330658},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.45059096813201904},{"id":"https://openalex.org/C74426580","wikidata":"https://www.wikidata.org/wiki/Q719484","display_name":"Memory map","level":3,"score":0.4368826746940613},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4276025891304016},{"id":"https://openalex.org/C41036726","wikidata":"https://www.wikidata.org/wiki/Q844824","display_name":"Physical address","level":3,"score":0.4203537404537201},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3508259057998657},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.26082372665405273},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.23875969648361206}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccd.2016.7753270","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2016.7753270","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE 34th International Conference on Computer Design (ICCD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W1975698617","https://openalex.org/W1985210871","https://openalex.org/W2013626513","https://openalex.org/W2067510835","https://openalex.org/W2077940408","https://openalex.org/W2082375193","https://openalex.org/W2082437541","https://openalex.org/W2082982763","https://openalex.org/W2088895605","https://openalex.org/W2092212481","https://openalex.org/W2102449048","https://openalex.org/W2104094932","https://openalex.org/W2115172404","https://openalex.org/W2120829734","https://openalex.org/W2131413854","https://openalex.org/W2135089498","https://openalex.org/W2148797773","https://openalex.org/W2152659795","https://openalex.org/W2162639668","https://openalex.org/W2164264749","https://openalex.org/W2165284728","https://openalex.org/W2166620913","https://openalex.org/W2916411819","https://openalex.org/W3139689176","https://openalex.org/W6683899152"],"related_works":["https://openalex.org/W2782503170","https://openalex.org/W1975698617","https://openalex.org/W2145484885","https://openalex.org/W4317815260","https://openalex.org/W2096506606","https://openalex.org/W2117533242","https://openalex.org/W2606565524","https://openalex.org/W2126827366","https://openalex.org/W4295235956","https://openalex.org/W2119548576"],"abstract_inverted_index":{"With":[0,177],"the":[1,10,18,32,55,64,72,81,86,104,110,123,137,141,154,157,164,178,185,189,199],"advent":[2],"of":[3,12,51,58,63,83,88,106,166,191],"stacked":[4],"memory":[5,8,13,20,23,41,46,52,60,77,94,107,128,142],"and":[6,29,85,114,144,182],"new":[7],"architectures,":[9],"heterogeneity":[11],"has":[14,25],"been":[15],"increasing.":[16],"In":[17,148],"diverse":[19],"technologies,":[21],"each":[22],"architecture":[24],"its":[26],"own":[27],"advantages":[28],"weaknesses.":[30],"Considering":[31],"trade-offs,":[33],"future":[34],"systems":[35],"are":[36],"expected":[37],"to":[38,121,140,150,198],"support":[39],"multiple":[40],"architectures":[42,53,95,143],"with":[43],"a":[44,116,131],"hybrid":[45],"system.":[47],"However,":[48],"such":[49,151],"diversity":[50,108],"complicates":[54],"performance":[56,190],"optimization":[57],"on-chip":[59],"hierarchy.":[61],"One":[62],"key":[65],"components":[66],"affected":[67],"by":[68,163,193],"this":[69],"trend":[70],"is":[71],"hardware":[73],"prefetcher.":[74],"The":[75],"available":[76],"bandwidth":[78,175],"highly":[79],"affects":[80],"effectiveness":[82],"prefetchers,":[84],"aggressiveness":[87,125],"prefetchers":[89,172],"must":[90],"be":[91],"tuned":[92],"for":[93,159,202],"as":[96,98],"well":[97],"application":[99,145],"behaviors.":[100],"This":[101],"paper":[102],"investigates":[103],"effect":[105],"on":[109,195],"prefetcher":[111],"parameter":[112,118,180],"selection,":[113],"proposes":[115],"dynamic":[117,179],"search":[119,181],"mechanism":[120,138],"adjust":[122],"prefetch":[124,204],"under":[126],"various":[127],"architectures.":[129],"Using":[130],"general":[132],"hill":[133],"climbing":[134],"scheme":[135,201],"periodically,":[136],"adapts":[139],"behaviors":[146],"effectively.":[147],"addition":[149],"automatic":[152],"tuning,":[153],"study":[155],"improves":[156,188],"solution":[158],"cache":[160],"pollution":[161,183],"exacerbated":[162],"increase":[165],"speculative":[167],"data":[168],"from":[169],"more":[170],"aggressive":[171],"in":[173],"higher":[174],"memory.":[176],"mitigation,":[184],"proposed":[186],"framework":[187],"applications":[192],"12.4%":[194],"average":[196],"compared":[197],"prior":[200],"tuning":[203],"parameters.":[205]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
