{"id":"https://openalex.org/W1701908161","doi":"https://doi.org/10.1109/iccd.2015.7357183","title":"FPGA-SPICE: A simulation-based power estimation framework for FPGAs","display_name":"FPGA-SPICE: A simulation-based power estimation framework for FPGAs","publication_year":2015,"publication_date":"2015-10-01","ids":{"openalex":"https://openalex.org/W1701908161","doi":"https://doi.org/10.1109/iccd.2015.7357183","mag":"1701908161"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.2015.7357183","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2015.7357183","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 33rd IEEE International Conference on Computer Design (ICCD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://infoscience.epfl.ch/record/211006","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103004961","display_name":"Xifan Tang","orcid":"https://orcid.org/0000-0003-2203-3981"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":true,"raw_author_name":"Xifan Tang","raw_affiliation_strings":["Integrated Systems Laboratory (LSI), Ecole Poly technique Federale de Lausanne (EPFL), Lausanne, Vaud, Switzerland","Integrated Systems Laboratory (LSI), \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Lausanne, Vaud, Switzerland#TAB#"],"affiliations":[{"raw_affiliation_string":"Integrated Systems Laboratory (LSI), Ecole Poly technique Federale de Lausanne (EPFL), Lausanne, Vaud, Switzerland","institution_ids":["https://openalex.org/I5124864"]},{"raw_affiliation_string":"Integrated Systems Laboratory (LSI), \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Lausanne, Vaud, Switzerland#TAB#","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002568331","display_name":"Pierre\u2010Emmanuel Gaillardon","orcid":"https://orcid.org/0000-0003-3634-3999"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Pierre-Emmanuel Gaillardon","raw_affiliation_strings":["Integrated Systems Laboratory (LSI), Ecole Poly technique Federale de Lausanne (EPFL), Lausanne, Vaud, Switzerland","Integrated Systems Laboratory (LSI), \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Lausanne, Vaud, Switzerland#TAB#"],"affiliations":[{"raw_affiliation_string":"Integrated Systems Laboratory (LSI), Ecole Poly technique Federale de Lausanne (EPFL), Lausanne, Vaud, Switzerland","institution_ids":["https://openalex.org/I5124864"]},{"raw_affiliation_string":"Integrated Systems Laboratory (LSI), \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Lausanne, Vaud, Switzerland#TAB#","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5072927296","display_name":"Giovanni De Micheli","orcid":"https://orcid.org/0000-0002-7827-3215"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Giovanni De Micheli","raw_affiliation_strings":["Integrated Systems Laboratory (LSI), Ecole Poly technique Federale de Lausanne (EPFL), Lausanne, Vaud, Switzerland","Integrated Systems Laboratory (LSI), \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Lausanne, Vaud, Switzerland#TAB#"],"affiliations":[{"raw_affiliation_string":"Integrated Systems Laboratory (LSI), Ecole Poly technique Federale de Lausanne (EPFL), Lausanne, Vaud, Switzerland","institution_ids":["https://openalex.org/I5124864"]},{"raw_affiliation_string":"Integrated Systems Laboratory (LSI), \u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne (EPFL), Lausanne, Vaud, Switzerland#TAB#","institution_ids":["https://openalex.org/I5124864"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5103004961"],"corresponding_institution_ids":["https://openalex.org/I5124864"],"apc_list":null,"apc_paid":null,"fwci":2.6531,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.89490696,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"696","last_page":"703"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7730037569999695},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.6820018887519836},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6690428853034973},{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.6008778810501099},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.500795841217041},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.41911664605140686},{"id":"https://openalex.org/keywords/multiplexer","display_name":"Multiplexer","score":0.4121689796447754},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3323567807674408},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.2679327726364136},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18274006247520447},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.11889836192131042}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7730037569999695},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.6820018887519836},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6690428853034973},{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.6008778810501099},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.500795841217041},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.41911664605140686},{"id":"https://openalex.org/C70970002","wikidata":"https://www.wikidata.org/wiki/Q189434","display_name":"Multiplexer","level":3,"score":0.4121689796447754},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3323567807674408},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.2679327726364136},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18274006247520447},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.11889836192131042},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iccd.2015.7357183","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2015.7357183","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 33rd IEEE International Conference on Computer Design (ICCD)","raw_type":"proceedings-article"},{"id":"pmh:oai:infoscience.epfl.ch:211006","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/211006","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Text"}],"best_oa_location":{"id":"pmh:oai:infoscience.epfl.ch:211006","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/211006","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Text"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.6499999761581421}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W136812135","https://openalex.org/W1480183640","https://openalex.org/W1523051745","https://openalex.org/W1967128905","https://openalex.org/W1990067642","https://openalex.org/W2030765577","https://openalex.org/W2072249022","https://openalex.org/W2095558812","https://openalex.org/W2096424065","https://openalex.org/W2104812993","https://openalex.org/W2105281355","https://openalex.org/W2116094656","https://openalex.org/W2120428171","https://openalex.org/W2128473621","https://openalex.org/W2138383740","https://openalex.org/W2141248063","https://openalex.org/W2155316178","https://openalex.org/W3143002681","https://openalex.org/W3152435103","https://openalex.org/W4243164749"],"related_works":["https://openalex.org/W2552408918","https://openalex.org/W4243305727","https://openalex.org/W2145339442","https://openalex.org/W3217774925","https://openalex.org/W1603048359","https://openalex.org/W3149311759","https://openalex.org/W2117300767","https://openalex.org/W2024574431","https://openalex.org/W1972355764","https://openalex.org/W1993197222"],"abstract_inverted_index":{"Mainstream":[0],"Field":[1],"Programmable":[2],"Gate":[3],"Array":[4],"(FPGA)":[5],"power":[6,17,20,62,69,78,100,116,215],"estimation":[7,14,79,101],"tools":[8],"are":[9,51],"based":[10],"on":[11],"probabilistic":[12],"activity":[13],"and":[15,113,135,251,259],"analytical":[16,61],"models.":[18],"The":[19],"consumption":[21],"of":[22,26,42,118,129,163,166,217,236,247],"the":[23,40,67,110,141,145,156,189,205,214,230,237,240,248,252,257],"programmable":[24],"resources":[25],"FPGAs":[27,43],"is":[28],"highly":[29,37],"sensitive":[30],"to":[31,35,57,109,204,212],"their":[32,36],"configurations.":[33],"Due":[34],"flexible":[38],"nature,":[39],"configurations":[41,112],"routing":[44,232,242],"multiplexers":[45],"or":[46,172],"Look":[47],"Up":[48],"Tables":[49],"(LUTs)":[50],"really":[52],"different":[53,127,223],"from":[54,256],"a":[55,76,167,198,218],"design":[56],"another":[58],"but":[59],"current":[60],"models":[63],"cannot":[64],"accurately":[65],"capture":[66],"associated":[68,143],"differences.":[70],"In":[71],"this":[72],"paper,":[73],"we":[74],"introduce":[75],"simulation-based":[77],"framework":[80],"for":[81,245],"FPGAs,":[82],"called":[83],"FPGA-SPICE,":[84],"which":[85,164,175],"supports":[86],"any":[87],"FPGA":[88,111,119,147,220],"architecture":[89,221,233,243],"that":[90,188,229],"can":[91,123,154,192],"be":[92,124],"described":[93],"with":[94,144,197],"an":[95],"architectural":[96],"description":[97],"language.":[98],"Our":[99],"engine":[102],"automatically":[103],"generates":[104],"accurate":[105],"SPICE":[106,121],"netlists":[107,142],"according":[108],"enables":[114],"precise":[115],"analysis":[117],"architectures.":[120],"testbenches":[122,139,158],"generated":[125],"at":[126,222],"level":[128],"complexity,":[130],"denoted":[131],"as":[132],"full-chip-level,":[133],"grid-level":[134,160],"component-level":[136,173],"testbenches.":[137],"Full-chip-level":[138],"dump":[140],"complete":[146,168],"fabric.":[148],"To":[149],"reduce":[150],"simulation":[151],"time,":[152],"FPGA-SPICE":[153,211],"split":[155],"full-chip-level":[157],"into":[159],"testbenches,":[161,174],"each":[162],"consisting":[165],"logic":[169],"block":[170],"netlist,":[171],"consider":[176],"individual":[177],"circuit":[178],"elements,":[179],"i.e.,":[180],"multiplexers,":[181],"LUTs,":[182],"flip-flops,":[183],"etc.,":[184],"separately.":[185],"We":[186,208],"show":[187,228],"grid/component-level":[190],"approach":[191],"achieve":[193],"14":[194],"\u00d7":[195],"speed-up":[196],"moderate":[199],"14%":[200],"accuracy":[201],"loss,":[202],"compared":[203],"full-chip":[206],"level.":[207],"also":[209],"use":[210],"study":[213],"characteristics":[216],"commercial":[219],"technology":[224],"nodes.":[225],"Experimental":[226],"results":[227],"global":[231],"consumes":[234],"50%":[235],"total":[238,249],"power,":[239,250],"local":[241],"claims":[244],"40%":[246],"remaining":[253],"10%":[254],"comes":[255],"LUTs":[258],"flip-flops.":[260]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":4},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":3}],"updated_date":"2026-03-25T13:04:00.132906","created_date":"2025-10-10T00:00:00"}