{"id":"https://openalex.org/W2220698963","doi":"https://doi.org/10.1109/iccd.2015.7357108","title":"SOP based logic synthesis for memristive IMPLY stateful logic","display_name":"SOP based logic synthesis for memristive IMPLY stateful logic","publication_year":2015,"publication_date":"2015-10-01","ids":{"openalex":"https://openalex.org/W2220698963","doi":"https://doi.org/10.1109/iccd.2015.7357108","mag":"2220698963"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.2015.7357108","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2015.7357108","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 33rd IEEE International Conference on Computer Design (ICCD)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5010444815","display_name":"Felipe S. Marranghello","orcid":"https://orcid.org/0000-0002-5368-6750"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Felipe S. Marranghello","raw_affiliation_strings":["PGMICRO, Federal University of Rio Grande do Sul, Porto Alegre, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"PGMICRO, Federal University of Rio Grande do Sul, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5105354099","display_name":"Vinicius Callegaro","orcid":null},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Vinicius Callegaro","raw_affiliation_strings":["PPGC, Federal University of Rio Grande do Sul, Porto Alegre, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"PPGC, Federal University of Rio Grande do Sul, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065397615","display_name":"Andr\u00e9 I. Reis","orcid":"https://orcid.org/0000-0002-3118-8160"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Andre I. Reis","raw_affiliation_strings":["PPGC, Federal University of Rio Grande do Sul, Porto Alegre, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"PPGC, Federal University of Rio Grande do Sul, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5090563366","display_name":"Renato P. Ribas","orcid":"https://orcid.org/0000-0002-9895-7489"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Renato P. Ribas","raw_affiliation_strings":["PPGC, Federal University of Rio Grande do Sul, Porto Alegre, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"PPGC, Federal University of Rio Grande do Sul, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I130442723"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"228","last_page":"235"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9948999881744385,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/stateful-firewall","display_name":"Stateful firewall","score":0.8605695962905884},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5900587439537048},{"id":"https://openalex.org/keywords/memristor","display_name":"Memristor","score":0.5567521452903748},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.49362289905548096},{"id":"https://openalex.org/keywords/expression","display_name":"Expression (computer science)","score":0.4845384955406189},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.46784576773643494},{"id":"https://openalex.org/keywords/work","display_name":"Work (physics)","score":0.4112709164619446},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.40024036169052124},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.370200514793396},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3463199734687805},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.2763715386390686},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.13832134008407593},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11479371786117554},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.1078207790851593},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.08577951788902283}],"concepts":[{"id":"https://openalex.org/C22927095","wikidata":"https://www.wikidata.org/wiki/Q1784206","display_name":"Stateful firewall","level":3,"score":0.8605695962905884},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5900587439537048},{"id":"https://openalex.org/C150072547","wikidata":"https://www.wikidata.org/wiki/Q212923","display_name":"Memristor","level":2,"score":0.5567521452903748},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.49362289905548096},{"id":"https://openalex.org/C90559484","wikidata":"https://www.wikidata.org/wiki/Q778379","display_name":"Expression (computer science)","level":2,"score":0.4845384955406189},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.46784576773643494},{"id":"https://openalex.org/C18762648","wikidata":"https://www.wikidata.org/wiki/Q42213","display_name":"Work (physics)","level":2,"score":0.4112709164619446},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.40024036169052124},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.370200514793396},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3463199734687805},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.2763715386390686},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.13832134008407593},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11479371786117554},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.1078207790851593},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.08577951788902283},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C158379750","wikidata":"https://www.wikidata.org/wiki/Q214111","display_name":"Network packet","level":2,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccd.2015.7357108","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2015.7357108","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 33rd IEEE International Conference on Computer Design (ICCD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320321091","display_name":"Coordena\u00e7\u00e3o de Aperfei\u00e7oamento de Pessoal de N\u00edvel Superior","ror":"https://ror.org/00x0ma614"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1994082062","https://openalex.org/W2004640050","https://openalex.org/W2018094844","https://openalex.org/W2025674646","https://openalex.org/W2025828180","https://openalex.org/W2044645265","https://openalex.org/W2059126686","https://openalex.org/W2063730370","https://openalex.org/W2066280488","https://openalex.org/W2067472652","https://openalex.org/W2083298190","https://openalex.org/W2112181056","https://openalex.org/W2122148191","https://openalex.org/W2155952358","https://openalex.org/W2162651880","https://openalex.org/W2170095368","https://openalex.org/W2220593183","https://openalex.org/W3143673400","https://openalex.org/W4231924340"],"related_works":["https://openalex.org/W2098419840","https://openalex.org/W1966764473","https://openalex.org/W2789349722","https://openalex.org/W1985308002","https://openalex.org/W2614722573","https://openalex.org/W2121963733","https://openalex.org/W1977171228","https://openalex.org/W2059422871","https://openalex.org/W2766377030","https://openalex.org/W2041787842"],"abstract_inverted_index":{"This":[0],"work":[1,24,42],"presents":[2],"an":[3],"efficient":[4],"algorithm":[5],"to":[6,35,40],"obtain":[7],"a":[8,14,44],"material":[9],"implication":[10],"(IMPLY)":[11],"expression":[12,19],"from":[13],"sum-of-products":[15],"(SOP).":[16],"The":[17,26],"resulting":[18],"is":[20],"computable":[21],"with":[22,33],"two":[23],"memristors.":[25],"proposed":[27,56],"method":[28],"has":[29],"linear":[30],"time":[31],"complexity":[32],"respect":[34],"the":[36,47,55],"SOP":[37],"size.":[38],"Comparison":[39],"previous":[41],"shows":[43],"reduction":[45],"on":[46],"average":[48],"number":[49],"of":[50],"IMPLY":[51],"operations":[52],"when":[53],"applying":[54],"method.":[57]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":4},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":4}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}