{"id":"https://openalex.org/W2202619809","doi":"https://doi.org/10.1109/iccd.2015.7357082","title":"SI-SMART: Functional test generation for RTL circuits using loop abstraction and learning recurrence relationships","display_name":"SI-SMART: Functional test generation for RTL circuits using loop abstraction and learning recurrence relationships","publication_year":2015,"publication_date":"2015-10-01","ids":{"openalex":"https://openalex.org/W2202619809","doi":"https://doi.org/10.1109/iccd.2015.7357082","mag":"2202619809"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.2015.7357082","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2015.7357082","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 33rd IEEE International Conference on Computer Design (ICCD)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5030074420","display_name":"Prateek Puri","orcid":null},"institutions":[{"id":"https://openalex.org/I859038795","display_name":"Virginia Tech","ror":"https://ror.org/02smfhw86","country_code":"US","type":"education","lineage":["https://openalex.org/I859038795"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Prateek Puri","raw_affiliation_strings":["Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, VA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, VA, USA","institution_ids":["https://openalex.org/I859038795"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5091060531","display_name":"Michael S. Hsiao Bradley","orcid":null},"institutions":[{"id":"https://openalex.org/I859038795","display_name":"Virginia Tech","ror":"https://ror.org/02smfhw86","country_code":"US","type":"education","lineage":["https://openalex.org/I859038795"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Michael S. Hsiao Bradley","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Virginia Polytechnic Institute and State University, Blacksburg, VA, US"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Virginia Polytechnic Institute and State University, Blacksburg, VA, US","institution_ids":["https://openalex.org/I859038795"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I859038795"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"38","last_page":"45"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10743","display_name":"Software Testing and Debugging Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/loop-unrolling","display_name":"Loop unrolling","score":0.7478129267692566},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7299350500106812},{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.7263359427452087},{"id":"https://openalex.org/keywords/symbolic-execution","display_name":"Symbolic execution","score":0.6173127889633179},{"id":"https://openalex.org/keywords/satisfiability-modulo-theories","display_name":"Satisfiability modulo theories","score":0.615512490272522},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.521584689617157},{"id":"https://openalex.org/keywords/boolean-satisfiability-problem","display_name":"Boolean satisfiability problem","score":0.5138707160949707},{"id":"https://openalex.org/keywords/solver","display_name":"Solver","score":0.5128310322761536},{"id":"https://openalex.org/keywords/model-checking","display_name":"Model checking","score":0.4700419306755066},{"id":"https://openalex.org/keywords/control-flow-graph","display_name":"Control flow graph","score":0.45762547850608826},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.45433029532432556},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.44968926906585693},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.4490523934364319},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4486258327960968},{"id":"https://openalex.org/keywords/abstraction","display_name":"Abstraction","score":0.4409111738204956},{"id":"https://openalex.org/keywords/boolean-function","display_name":"Boolean function","score":0.4302920699119568},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.42508867383003235},{"id":"https://openalex.org/keywords/generator","display_name":"Generator (circuit theory)","score":0.4119296073913574},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.35163649916648865},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3047040104866028},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2377520203590393},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.20193982124328613},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.1656910479068756},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.13541942834854126},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.13304033875465393}],"concepts":[{"id":"https://openalex.org/C76970557","wikidata":"https://www.wikidata.org/wiki/Q1869750","display_name":"Loop unrolling","level":3,"score":0.7478129267692566},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7299350500106812},{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.7263359427452087},{"id":"https://openalex.org/C2779639559","wikidata":"https://www.wikidata.org/wiki/Q7661178","display_name":"Symbolic execution","level":3,"score":0.6173127889633179},{"id":"https://openalex.org/C164155591","wikidata":"https://www.wikidata.org/wiki/Q2067766","display_name":"Satisfiability modulo theories","level":2,"score":0.615512490272522},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.521584689617157},{"id":"https://openalex.org/C6943359","wikidata":"https://www.wikidata.org/wiki/Q875276","display_name":"Boolean satisfiability problem","level":2,"score":0.5138707160949707},{"id":"https://openalex.org/C2778770139","wikidata":"https://www.wikidata.org/wiki/Q1966904","display_name":"Solver","level":2,"score":0.5128310322761536},{"id":"https://openalex.org/C110251889","wikidata":"https://www.wikidata.org/wiki/Q1569697","display_name":"Model checking","level":2,"score":0.4700419306755066},{"id":"https://openalex.org/C27458966","wikidata":"https://www.wikidata.org/wiki/Q1187693","display_name":"Control flow graph","level":2,"score":0.45762547850608826},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.45433029532432556},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.44968926906585693},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.4490523934364319},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4486258327960968},{"id":"https://openalex.org/C124304363","wikidata":"https://www.wikidata.org/wiki/Q673661","display_name":"Abstraction","level":2,"score":0.4409111738204956},{"id":"https://openalex.org/C187455244","wikidata":"https://www.wikidata.org/wiki/Q942353","display_name":"Boolean function","level":2,"score":0.4302920699119568},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.42508867383003235},{"id":"https://openalex.org/C2780992000","wikidata":"https://www.wikidata.org/wiki/Q17016113","display_name":"Generator (circuit theory)","level":3,"score":0.4119296073913574},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.35163649916648865},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3047040104866028},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2377520203590393},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.20193982124328613},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.1656910479068756},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.13541942834854126},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.13304033875465393},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccd.2015.7357082","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2015.7357082","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 33rd IEEE International Conference on Computer Design (ICCD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":30,"referenced_works":["https://openalex.org/W17724786","https://openalex.org/W1480909796","https://openalex.org/W1982205631","https://openalex.org/W1999024797","https://openalex.org/W2000621750","https://openalex.org/W2058214764","https://openalex.org/W2074371713","https://openalex.org/W2081423733","https://openalex.org/W2102691476","https://openalex.org/W2109276114","https://openalex.org/W2109364787","https://openalex.org/W2111979321","https://openalex.org/W2125213524","https://openalex.org/W2130749203","https://openalex.org/W2132673604","https://openalex.org/W2133862387","https://openalex.org/W2143208164","https://openalex.org/W2150764159","https://openalex.org/W2152710595","https://openalex.org/W2155298431","https://openalex.org/W2171106218","https://openalex.org/W3145288617","https://openalex.org/W4235775353","https://openalex.org/W4244517018","https://openalex.org/W4250336630","https://openalex.org/W6600689400","https://openalex.org/W6676590341","https://openalex.org/W6679586440","https://openalex.org/W6679923517","https://openalex.org/W6682494195"],"related_works":["https://openalex.org/W2498204369","https://openalex.org/W2543290882","https://openalex.org/W1964556228","https://openalex.org/W2132665983","https://openalex.org/W2000778050","https://openalex.org/W2165782627","https://openalex.org/W4389166667","https://openalex.org/W2146894108","https://openalex.org/W4388747729","https://openalex.org/W2547468435"],"abstract_inverted_index":{"We":[0],"present":[1,75],"SI-SMART,":[2],"a":[3,124],"hybrid":[4],"Swarm":[5,129],"Intelligence":[6],"and":[7,82,112,132,172],"Satisfiability":[8],"Modulo":[9],"theory":[10],"based":[11,26],"Automatic":[12],"Register":[13],"Transfer":[14],"level":[15],"test":[16,44,80,169],"generator.":[17],"Traditional":[18],"Bounded":[19],"Model":[20],"Checking":[21],"(BMC)":[22],"or":[23,94],"symbolic":[24],"execution":[25,173],"methods":[27],"depend":[28],"upon":[29],"multi-cycle":[30],"circuit":[31],"unrolling/analysis":[32],"for":[33],"stimuli":[34],"generation.":[35],"The":[36],"presence":[37],"of":[38,63,126,150],"loops":[39,74],"in":[40,51,76,159,166],"the":[41,64,77,86,90,97,110,113,140],"design":[42,53,78],"under":[43,79],"(DUT)":[45,81],"typically":[46],"limits":[47],"such":[48],"methods,":[49],"resulting":[50],"lower":[52],"coverage.":[54],"SI-SMART":[55,143],"tackles":[56],"this":[57],"problem":[58],"by":[59,72],"eliminating":[60],"explicit":[61],"unrolling":[62],"control":[65],"flow":[66],"graph":[67],"(CFG).":[68],"This":[69,116],"is":[70,104,119,144,157],"achieved":[71,158],"abstracting":[73],"attempting":[83],"to":[84,106,123,136,138],"learn":[85],"recurrence":[87],"relations":[88],"among":[89],"variables":[91],"that":[92],"directly":[93],"indirectly":[95],"affect":[96],"target":[98,114],"branch":[99,155,167],"condition.":[100],"An":[101],"SMT":[102],"solver":[103],"used":[105],"find":[107],"correlations":[108],"between":[109],"inputs":[111],"branches.":[115,142],"learned":[117],"knowledge":[118],"later":[120],"fed":[121],"back":[122],"combination":[125],"Binary":[127],"Particle":[128],"Optimization":[130],"(BPSO)":[131],"Hooke":[133],"Jeeves":[134],"method":[135],"attempt":[137],"reach":[139],"uncovered":[141],"evaluated":[145],"on":[146],"several":[147],"difficult":[148],"variants":[149],"ITC99":[151],"benchmark":[152],"circuits.":[153],"100%":[154],"coverage":[156],"almost":[160],"all":[161],"circuits":[162],"with":[163],"significant":[164],"improvement":[165],"coverage,":[168],"sequence":[170],"lengths":[171],"times":[174],"over":[175],"existing":[176],"methods.":[177]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}