{"id":"https://openalex.org/W2023550229","doi":"https://doi.org/10.1109/iccd.2014.6974675","title":"The ITRS MPU and SOC system drivers: Calibration and implications for design-based equivalent scaling in the roadmap","display_name":"The ITRS MPU and SOC system drivers: Calibration and implications for design-based equivalent scaling in the roadmap","publication_year":2014,"publication_date":"2014-10-01","ids":{"openalex":"https://openalex.org/W2023550229","doi":"https://doi.org/10.1109/iccd.2014.6974675","mag":"2023550229"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.2014.6974675","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2014.6974675","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE 32nd International Conference on Computer Design (ICCD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5058532858","display_name":"Wei-Ting Jonas Chan","orcid":null},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Wei-Ting Jonas Chan","raw_affiliation_strings":["ECE","ECE, UC San Diego, La Jolla, CA 92093, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ECE","institution_ids":[]},{"raw_affiliation_string":"ECE, UC San Diego, La Jolla, CA 92093, USA","institution_ids":["https://openalex.org/I36258959"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073558386","display_name":"Andrew B. Kahng","orcid":"https://orcid.org/0000-0002-4490-5018"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]},{"id":"https://openalex.org/I4210103595","display_name":"La Jolla Alcohol Research","ror":"https://ror.org/00vvpe721","country_code":"US","type":"other","lineage":["https://openalex.org/I4210103595"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Andrew B. Kahng","raw_affiliation_strings":["CSE Departments, La Jolla, CA, USA","ECE","ECE, UC San Diego, La Jolla, CA 92093, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CSE Departments, La Jolla, CA, USA","institution_ids":["https://openalex.org/I4210103595"]},{"raw_affiliation_string":"ECE","institution_ids":[]},{"raw_affiliation_string":"ECE, UC San Diego, La Jolla, CA 92093, USA","institution_ids":["https://openalex.org/I36258959"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101615907","display_name":"Siddhartha Nath","orcid":"https://orcid.org/0000-0002-4848-3385"},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]},{"id":"https://openalex.org/I4210103595","display_name":"La Jolla Alcohol Research","ror":"https://ror.org/00vvpe721","country_code":"US","type":"other","lineage":["https://openalex.org/I4210103595"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Siddhartha Nath","raw_affiliation_strings":["CSE Departments, La Jolla, CA, USA","CSE Departments, UC San Diego, La Jolla, CA 92093, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CSE Departments, La Jolla, CA, USA","institution_ids":["https://openalex.org/I4210103595"]},{"raw_affiliation_string":"CSE Departments, UC San Diego, La Jolla, CA 92093, USA","institution_ids":["https://openalex.org/I36258959"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5031723646","display_name":"Ichiro Yamamoto","orcid":null},"institutions":[{"id":"https://openalex.org/I162282272","display_name":"ROHM","ror":"https://ror.org/00vttj605","country_code":"JP","type":"company","lineage":["https://openalex.org/I162282272"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Ichiro Yamamoto","raw_affiliation_strings":["Rohm Co., Ltd., Shinyokohama, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Rohm Co., Ltd., Shinyokohama, Japan","institution_ids":["https://openalex.org/I162282272"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.8906,"has_fulltext":false,"cited_by_count":18,"citation_normalized_percentile":{"value":0.85337993,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"153","last_page":"160"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.6296752095222473},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5224153995513916},{"id":"https://openalex.org/keywords/design-for-manufacturability","display_name":"Design for manufacturability","score":0.4977271854877472},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.4938848614692688},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.43530339002609253},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.42622363567352295},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.42110562324523926},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.41636067628860474},{"id":"https://openalex.org/keywords/technology-roadmap","display_name":"Technology roadmap","score":0.4139168858528137},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.30569329857826233},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.20240327715873718}],"concepts":[{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.6296752095222473},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5224153995513916},{"id":"https://openalex.org/C62064638","wikidata":"https://www.wikidata.org/wiki/Q553878","display_name":"Design for manufacturability","level":2,"score":0.4977271854877472},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.4938848614692688},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.43530339002609253},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.42622363567352295},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.42110562324523926},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.41636067628860474},{"id":"https://openalex.org/C2780156850","wikidata":"https://www.wikidata.org/wiki/Q2144097","display_name":"Technology roadmap","level":2,"score":0.4139168858528137},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.30569329857826233},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.20240327715873718},{"id":"https://openalex.org/C162853370","wikidata":"https://www.wikidata.org/wiki/Q39809","display_name":"Marketing","level":1,"score":0.0},{"id":"https://openalex.org/C144133560","wikidata":"https://www.wikidata.org/wiki/Q4830453","display_name":"Business","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccd.2014.6974675","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2014.6974675","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE 32nd International Conference on Computer Design (ICCD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6499999761581421,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1699715921","https://openalex.org/W1948403229","https://openalex.org/W2042479232","https://openalex.org/W2042536271","https://openalex.org/W2045647383","https://openalex.org/W2060631289","https://openalex.org/W2073992829","https://openalex.org/W2098286658","https://openalex.org/W2213561950","https://openalex.org/W2294226777","https://openalex.org/W6665670167","https://openalex.org/W7046331890"],"related_works":["https://openalex.org/W2060210001","https://openalex.org/W2388589331","https://openalex.org/W1569991298","https://openalex.org/W2545489593","https://openalex.org/W4246351405","https://openalex.org/W1970762549","https://openalex.org/W2549099758","https://openalex.org/W4234083032","https://openalex.org/W1573321145","https://openalex.org/W2366713167"],"abstract_inverted_index":{"The":[0,146,161,188],"system":[1,51,166],"driver":[2,52,167],"models":[3,53,71,87,112,168,304],"for":[4,15,72,113,157],"microprocessor":[5],"(MPU)":[6],"and":[7,32,49,75,81,108,116,129,138,225,276,282,302],"system-on-chip":[8],"(SOC)":[9],"in":[10,45,143,284,305,324],"the":[11,20,46,56,61,73,79,89,96,114,122,130,158,193,246,262,274,285,298,306,309,325],"International":[12],"Technology":[13],"Roadmap":[14],"Semiconductors":[16],"[21]":[17],"(ITRS)":[18],"determine":[19],"roadmap":[21],"of":[22,55,60,78,126,133,165,208,228,248,280,297],"underlying":[23],"technology":[24],"requirements":[25],"across":[26],"devices,":[27],"patterning,":[28],"interconnect,":[29],"test,":[30],"design":[31,234],"other":[33,139],"semiconductor":[34,263],"supplier":[35],"industries.":[36],"In":[37],"this":[38,254],"paper,":[39],"we":[40,120,291],"describe":[41,102,252],"several":[42],"fundamental":[43],"changes":[44,273],"ITRS":[47,163,286],"MPU":[48,80,115,127],"SOC":[50,82,117,144,148,159],"as":[54,175,177,221,223,294],"recently-released":[57],"2013":[58,162,307],"edition":[59],"roadmap.":[62,327],"We":[63,100,251],"first":[64],"present":[65],"new":[66],"A-factor":[67],"(i.e.,":[68],"layout":[69,219],"density)":[70],"logic":[74],"memory":[76],"components":[77],"drivers;":[83],"these":[84],"updated":[85,103,147,299],"density":[86,206,249],"comprehend":[88],"industry's":[90],"shift":[91],"to":[92,215,237,245],"FinFET":[93],"devices":[94],"below":[95],"foundry":[97,173],"20nm":[98],"node.":[99],"also":[101,243],"architectural,":[104],"total":[105,109],"chip":[106,110],"area,":[107],"power":[111,155,277,303,317],"drivers.":[118],"Notably,":[119],"model":[121,150,189,278],"growing":[123,131],"uncore":[124],"portion":[125],"products,":[128],"presence":[132],"graphic":[134],"processing":[135],"units":[136],"(GPUs)":[137],"peripheral":[140],"cores":[141],"(PEs)":[142],"architectures.":[145],"architectural":[149],"enables":[151],"more":[152,315],"realistic":[153],"scenario-based":[154],"modeling":[156],"driver.":[160],"update":[164],"embodies":[169],"extensive":[170],"calibration":[171,190],"with":[172,197],"data":[174],"well":[176,222],"product":[178],"structural":[179],"analysis":[180,185],"reports":[181],"from":[182],"a":[183,198,295,313],"leading":[184],"firm":[186],"(Chipworks).":[187],"reveals":[191],"that":[192,293],"industry":[194,264,310],"has":[195,212],"contended":[196],"\u201cscaling":[199],"gap\u201d":[200],"since":[201],"2008,":[202],"whereby":[203],"traditional":[204],"Moore's-Law":[205],"scaling":[207,255,269],"2\u00d7":[209],"per":[210],"node":[211],"failed":[213],"due":[214,236],"patterning":[216],"limitations":[217],"on":[218],"design,":[220],"manufacturability":[224],"performability":[226],"challenges":[227],"Metal-1":[229],"half-pitch":[230],"(M1HP)":[231],"scaling.":[232,250],"Growing":[233],"margins":[235],"reliability,":[238],"yield,":[239],"variability,":[240],"etc.":[241],"have":[242],"contributed":[244],"slowdown":[247],"how":[253],"gap":[256],"can":[257],"potentially":[258],"be":[259],"compensated":[260],"if":[261],"urgently":[265],"pursues":[266],"design-based":[267],"equivalent":[268],"(DES),":[270],"which":[271],"substantially":[272],"area":[275,301],"trajectories":[279],"MPUs":[281],"SOCs":[283],"System":[287],"Drivers":[288],"Chapter.":[289],"Finally,":[290],"note":[292],"consequence":[296],"A-factor,":[300],"ITRS,":[308],"now":[311],"faces":[312],"20%":[314],"daunting":[316],"management":[318],"challenge":[319],"than":[320],"had":[321],"been":[322],"predicted":[323],"2011":[326]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}