{"id":"https://openalex.org/W1995373617","doi":"https://doi.org/10.1109/iccd.2014.6974660","title":"Efficient design of FIR filters using hybrid multiple constant multiplications on FPGA","display_name":"Efficient design of FIR filters using hybrid multiple constant multiplications on FPGA","publication_year":2014,"publication_date":"2014-10-01","ids":{"openalex":"https://openalex.org/W1995373617","doi":"https://doi.org/10.1109/iccd.2014.6974660","mag":"1995373617"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.2014.6974660","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2014.6974660","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE 32nd International Conference on Computer Design (ICCD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5089933848","display_name":"Levent Aksoy","orcid":"https://orcid.org/0000-0001-6129-9657"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"Levent Aksoy","raw_affiliation_strings":["INESC-ID, Lisbon, Portugal"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"INESC-ID, Lisbon, Portugal","institution_ids":["https://openalex.org/I121345201"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002334825","display_name":"Paulo Flores","orcid":"https://orcid.org/0000-0003-2970-3589"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]},{"id":"https://openalex.org/I141596103","display_name":"University of Lisbon","ror":"https://ror.org/01c27hj86","country_code":"PT","type":"education","lineage":["https://openalex.org/I141596103"]},{"id":"https://openalex.org/I203847022","display_name":"Instituto Polit\u00e9cnico de Lisboa","ror":"https://ror.org/04ea70f07","country_code":"PT","type":"education","lineage":["https://openalex.org/I203847022"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"Paulo Flores","raw_affiliation_strings":["INESC-ID, Lisbon, Portugal","Instituto Superior T\u00e9cnico, Universidade de Lisboa, Lisbon, Portugal"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"INESC-ID, Lisbon, Portugal","institution_ids":["https://openalex.org/I121345201"]},{"raw_affiliation_string":"Instituto Superior T\u00e9cnico, Universidade de Lisboa, Lisbon, Portugal","institution_ids":["https://openalex.org/I203847022","https://openalex.org/I141596103"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5039448613","display_name":"Jos\u00e9 Monteiro","orcid":"https://orcid.org/0000-0003-0603-2268"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]},{"id":"https://openalex.org/I141596103","display_name":"University of Lisbon","ror":"https://ror.org/01c27hj86","country_code":"PT","type":"education","lineage":["https://openalex.org/I141596103"]},{"id":"https://openalex.org/I203847022","display_name":"Instituto Polit\u00e9cnico de Lisboa","ror":"https://ror.org/04ea70f07","country_code":"PT","type":"education","lineage":["https://openalex.org/I203847022"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"Jose Monteiro","raw_affiliation_strings":["INESC-ID, Lisbon, Portugal","Instituto Superior T\u00e9cnico, Universidade de Lisboa, Lisbon, Portugal"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"INESC-ID, Lisbon, Portugal","institution_ids":["https://openalex.org/I121345201"]},{"raw_affiliation_string":"Instituto Superior T\u00e9cnico, Universidade de Lisboa, Lisbon, Portugal","institution_ids":["https://openalex.org/I203847022","https://openalex.org/I141596103"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.7692,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.84685199,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"48","issue":null,"first_page":"42","last_page":"47"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.8417155146598816},{"id":"https://openalex.org/keywords/multiplication","display_name":"Multiplication (music)","score":0.6137632131576538},{"id":"https://openalex.org/keywords/finite-impulse-response","display_name":"Finite impulse response","score":0.606679379940033},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5806012153625488},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5581190586090088},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.5144457817077637},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.4767383337020874},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.47357234358787537},{"id":"https://openalex.org/keywords/constant","display_name":"Constant (computer programming)","score":0.4609743654727936},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4421243667602539},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.38139304518699646},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.3574974536895752},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.3141210377216339},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.18537360429763794}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.8417155146598816},{"id":"https://openalex.org/C2780595030","wikidata":"https://www.wikidata.org/wiki/Q3860309","display_name":"Multiplication (music)","level":2,"score":0.6137632131576538},{"id":"https://openalex.org/C198386975","wikidata":"https://www.wikidata.org/wiki/Q117785","display_name":"Finite impulse response","level":2,"score":0.606679379940033},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5806012153625488},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5581190586090088},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.5144457817077637},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.4767383337020874},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.47357234358787537},{"id":"https://openalex.org/C2777027219","wikidata":"https://www.wikidata.org/wiki/Q1284190","display_name":"Constant (computer programming)","level":2,"score":0.4609743654727936},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4421243667602539},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.38139304518699646},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3574974536895752},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.3141210377216339},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.18537360429763794},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccd.2014.6974660","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2014.6974660","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE 32nd International Conference on Computer Design (ICCD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1973656570","https://openalex.org/W2001254103","https://openalex.org/W2073419265","https://openalex.org/W2099181277","https://openalex.org/W2117373759","https://openalex.org/W2125716184","https://openalex.org/W2127856935","https://openalex.org/W2130846531","https://openalex.org/W2154656381","https://openalex.org/W2164339744","https://openalex.org/W2165837912","https://openalex.org/W2165858176","https://openalex.org/W4244479343","https://openalex.org/W6655894424","https://openalex.org/W6684055521"],"related_works":["https://openalex.org/W4390550886","https://openalex.org/W3217463396","https://openalex.org/W2790557758","https://openalex.org/W2516396101","https://openalex.org/W3204929712","https://openalex.org/W4295102875","https://openalex.org/W3082309838","https://openalex.org/W2352374383","https://openalex.org/W1980880153","https://openalex.org/W4313145068"],"abstract_inverted_index":{"The":[0],"multiple":[1],"constant":[2,63],"multiplication":[3,9],"(MCM)":[4],"block,":[5],"which":[6,81,161],"realizes":[7],"the":[8,39,43,50,70,108,125,137,145,167],"of":[10,41,46,56,72,95,110,139,142,155],"constants":[11],"by":[12],"a":[13,16,54,66,88,133,163],"variable,":[14],"is":[15],"ubiquitous":[17],"operation":[18],"in":[19,69,144,172],"digital":[20],"signal":[21],"processing":[22],"(DSP)":[23],"systems.":[24],"It":[25],"can":[26,128],"be":[27],"implemented":[28],"using":[29],"generic":[30,84],"multipliers":[31,57,143],"or":[32],"shifts":[33],"and":[34,136,158],"adders/subtractors.":[35],"This":[36],"paper":[37],"addresses":[38],"problem":[40],"finding":[42],"minimum":[44],"number":[45,55,141,154],"adders/subtractors":[47],"to":[48,60,107,149,165],"realize":[49,61],"MCM":[51,146],"block":[52,147],"while":[53],"are":[58],"available":[59],"some":[62],"multiplications.":[64],"Such":[65],"situation":[67],"appears":[68],"design":[71],"DSP":[73],"systems":[74],"on":[75],"field":[76],"programmable":[77],"gate":[78],"arrays":[79],"(FPGAs)":[80],"also":[82,114],"include":[83],"multipliers.":[85],"We":[86],"present":[87],"0-1":[89],"integer":[90],"linear":[91],"programming":[92],"(ILP)":[93],"formulation":[94],"this":[96,111],"problem,":[97,112],"yielding":[98],"an":[99,116,173],"exact":[100],"common":[101],"subexpression":[102],"elimination":[103],"(CSE)":[104],"method.":[105],"Due":[106],"NP-completeness":[109],"we":[113],"introduce":[115],"approximate":[117],"graph-based":[118],"(GB)":[119],"algorithm.":[120],"Experimental":[121],"results":[122],"show":[123],"that":[124,169],"proposed":[126],"methods":[127],"find":[129],"better":[130],"solutions":[131],"than":[132],"state-of-art":[134],"algorithm":[135],"use":[138],"different":[140,153],"leads":[148],"filter":[150],"designs":[151],"with":[152],"slices,":[156],"delay,":[157],"power":[159],"dissipation":[160],"enable":[162],"designer":[164],"choose":[166],"one":[168],"fits":[170],"best":[171],"application.":[174]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
