{"id":"https://openalex.org/W1991756281","doi":"https://doi.org/10.1109/iccd.2013.6657042","title":"Data placement in HPC architectures with heterogeneous off-chip memory","display_name":"Data placement in HPC architectures with heterogeneous off-chip memory","publication_year":2013,"publication_date":"2013-10-01","ids":{"openalex":"https://openalex.org/W1991756281","doi":"https://doi.org/10.1109/iccd.2013.6657042","mag":"1991756281"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.2013.6657042","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2013.6657042","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE 31st International Conference on Computer Design (ICCD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://hdl.handle.net/2117/27947","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5000690768","display_name":"Milan Pavlovi\u0107","orcid":"https://orcid.org/0000-0002-1047-1661"},"institutions":[{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]},{"id":"https://openalex.org/I2799803557","display_name":"Barcelona Supercomputing Center","ror":"https://ror.org/05sd8tv96","country_code":"ES","type":"facility","lineage":["https://openalex.org/I2799803557","https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":true,"raw_author_name":"Milan Pavlovic","raw_affiliation_strings":["Barcelona Supercomputing Center","Barcelona Supercomput. Center, Barcelona, Spain"],"affiliations":[{"raw_affiliation_string":"Barcelona Supercomputing Center","institution_ids":["https://openalex.org/I9617848","https://openalex.org/I2799803557"]},{"raw_affiliation_string":"Barcelona Supercomput. Center, Barcelona, Spain","institution_ids":["https://openalex.org/I2799803557"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039002632","display_name":"Nikola Puzovic","orcid":null},"institutions":[{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Nikola Puzovic","raw_affiliation_strings":["Universitat Polit\u00e8cnica de Catalunya","Univ. Politec. de Catalunya, Barcelona, Spain"],"affiliations":[{"raw_affiliation_string":"Universitat Polit\u00e8cnica de Catalunya","institution_ids":["https://openalex.org/I9617848"]},{"raw_affiliation_string":"Univ. Politec. de Catalunya, Barcelona, Spain","institution_ids":["https://openalex.org/I9617848"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5082472991","display_name":"Alex Ram\u00edrez","orcid":"https://orcid.org/0000-0003-3317-4616"},"institutions":[{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]},{"id":"https://openalex.org/I2799803557","display_name":"Barcelona Supercomputing Center","ror":"https://ror.org/05sd8tv96","country_code":"ES","type":"facility","lineage":["https://openalex.org/I2799803557","https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Alex Ramirez","raw_affiliation_strings":["Barcelona Supercomputing Center","Barcelona Supercomput. Center, Barcelona, Spain"],"affiliations":[{"raw_affiliation_string":"Barcelona Supercomputing Center","institution_ids":["https://openalex.org/I9617848","https://openalex.org/I2799803557"]},{"raw_affiliation_string":"Barcelona Supercomput. Center, Barcelona, Spain","institution_ids":["https://openalex.org/I2799803557"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5000690768"],"corresponding_institution_ids":["https://openalex.org/I2799803557","https://openalex.org/I9617848"],"apc_list":null,"apc_paid":null,"fwci":2.5372,"has_fulltext":false,"cited_by_count":19,"citation_normalized_percentile":{"value":0.88994144,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"193","last_page":"200"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10101","display_name":"Cloud Computing and Resource Management","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8117140531539917},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.6982547044754028},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.6178749799728394},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.5618297457695007},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5120692849159241},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.5059532523155212},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5056922435760498},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.47393709421157837},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.4446151852607727},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.43913328647613525},{"id":"https://openalex.org/keywords/flat-memory-model","display_name":"Flat memory model","score":0.42918848991394043},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.41737401485443115},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.40418174862861633},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.33654141426086426},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2763427495956421},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.10142427682876587}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8117140531539917},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.6982547044754028},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.6178749799728394},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.5618297457695007},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5120692849159241},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.5059532523155212},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5056922435760498},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.47393709421157837},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.4446151852607727},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.43913328647613525},{"id":"https://openalex.org/C57863822","wikidata":"https://www.wikidata.org/wiki/Q905488","display_name":"Flat memory model","level":4,"score":0.42918848991394043},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.41737401485443115},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.40418174862861633},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.33654141426086426},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2763427495956421},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.10142427682876587}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/iccd.2013.6657042","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2013.6657042","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE 31st International Conference on Computer Design (ICCD)","raw_type":"proceedings-article"},{"id":"pmh:oai:www.recercat.cat:2072/250145","is_oa":true,"landing_page_url":"http://hdl.handle.net/2117/27947","pdf_url":null,"source":{"id":"https://openalex.org/S4306402147","display_name":"RECERCAT (Consorci de Serveis Universitaris de Catalunya)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210090028","host_organization_name":"Consorci de Serveis Universitaris de Catalunya","host_organization_lineage":["https://openalex.org/I4210090028"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"","raw_type":"info:eu-repo/semantics/publishedVersion"},{"id":"pmh:oai:upcommons.upc.edu:2117/27947","is_oa":false,"landing_page_url":"https://hdl.handle.net/2117/27947","pdf_url":null,"source":{"id":"https://openalex.org/S4377196262","display_name":"UPCommons institutional repository (Universitat Polit\u00e8cnica de Catalunya)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I9617848","host_organization_name":"Universitat Polit\u00e8cnica de Catalunya","host_organization_lineage":["https://openalex.org/I9617848"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":{"id":"pmh:oai:www.recercat.cat:2072/250145","is_oa":true,"landing_page_url":"http://hdl.handle.net/2117/27947","pdf_url":null,"source":{"id":"https://openalex.org/S4306402147","display_name":"RECERCAT (Consorci de Serveis Universitaris de Catalunya)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210090028","host_organization_name":"Consorci de Serveis Universitaris de Catalunya","host_organization_lineage":["https://openalex.org/I4210090028"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"","raw_type":"info:eu-repo/semantics/publishedVersion"},"sustainable_development_goals":[{"score":0.8199999928474426,"display_name":"Reduced inequalities","id":"https://metadata.un.org/sdg/10"}],"awards":[{"id":"https://openalex.org/G4054932317","display_name":null,"funder_award_id":"TIN2012-34557","funder_id":"https://openalex.org/F4320323737","funder_display_name":"Ministerio de Ciencia y Tecnolog\u00eda"}],"funders":[{"id":"https://openalex.org/F4320323737","display_name":"Ministerio de Ciencia y Tecnolog\u00eda","ror":"https://ror.org/034900433"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W51775301","https://openalex.org/W171848175","https://openalex.org/W1564523715","https://openalex.org/W2037291093","https://openalex.org/W2042076387","https://openalex.org/W2046006184","https://openalex.org/W2048588974","https://openalex.org/W2074357625","https://openalex.org/W2088883656","https://openalex.org/W2091548290","https://openalex.org/W2095685483","https://openalex.org/W2102449048","https://openalex.org/W2104305170","https://openalex.org/W2112300321","https://openalex.org/W2131413854","https://openalex.org/W2146245483","https://openalex.org/W2156858199","https://openalex.org/W2189500040","https://openalex.org/W3108620309","https://openalex.org/W3139689176","https://openalex.org/W4239035626","https://openalex.org/W4285719527","https://openalex.org/W6633941944"],"related_works":["https://openalex.org/W2155373950","https://openalex.org/W2145210935","https://openalex.org/W2138825797","https://openalex.org/W2587873888","https://openalex.org/W3108993429","https://openalex.org/W4243618206","https://openalex.org/W3008068282","https://openalex.org/W1993089791","https://openalex.org/W2044064773","https://openalex.org/W2047684617"],"abstract_inverted_index":{"The":[0,14,33],"performance":[1,145,188],"of":[2,16,20,35,45,60,68,99,148,154],"HPC":[3,134,168],"applications":[4],"is":[5,190],"often":[6],"bounded":[7],"by":[8,146],"the":[9,18,43,61,72,76,80,84,97,152,166,174],"underlying":[10],"memory":[11,28,37,47,64,102,114,121,156,176],"system's":[12],"performance.":[13],"trend":[15],"increasing":[17],"number":[19,153],"cores":[21],"on":[22,58],"a":[23,112,124,193],"chip":[24],"imposes":[25],"even":[26],"higher":[27],"bandwidth":[29],"and":[30,93,140,151,158,182],"capacity":[31,82],"requirements.":[32],"limitations":[34],"traditional":[36],"technologies":[38],"are":[39],"pushing":[40],"research":[41],"in":[42,123],"direction":[44],"hybrid":[46,101,113,175],"systems":[48],"that,":[49],"besides":[50],"DRAM,":[51],"include":[52],"one":[53,67],"or":[54],"more":[55],"modules":[56,98,122],"based":[57],"some":[59],"higher-density":[62],"non-volatile":[63,155],"technologies,":[65],"where":[66],"them":[69],"will":[70,78],"provide":[71,79],"required":[73,81],"bandwidth,":[74],"while":[75],"other":[77],"for":[83],"application.":[85],"This":[86],"creates":[87],"many":[88],"challenges":[89],"with":[90,111,178],"data":[91,138],"placement":[92,139],"migration":[94,141,181],"policies":[95],"between":[96],"such":[100,129],"system.":[103,199],"In":[104],"this":[105],"paper,":[106],"we":[107,131],"propose":[108],"an":[109],"architecture":[110],"design":[115],"that":[116,173,189],"places":[117],"two":[118],"technologically":[119],"different":[120,137],"flat":[125],"address":[126],"space.":[127],"On":[128],"system,":[130],"evaluate":[132],"several":[133],"workloads":[135],"against":[136],"policies,":[142],"compare":[143],"their":[144],"means":[147],"execution":[149],"time":[150],"writes,":[157],"consider":[159],"how":[160],"it":[161],"can":[162,186],"be":[163],"applied":[164],"to":[165,192,196],"future":[167],"architectures.":[169],"Our":[170],"results":[171],"show":[172],"system":[177],"dynamic":[179],"page":[180],"limited":[183],"DRAM":[184],"capacity,":[185],"achieve":[187],"comparable":[191],"hypothetical,":[194],"hard":[195],"implement,":[197],"DRAM-only":[198]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2019,"cited_by_count":4},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":4},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":4},{"year":2014,"cited_by_count":1}],"updated_date":"2026-04-10T15:06:20.359241","created_date":"2025-10-10T00:00:00"}
