{"id":"https://openalex.org/W2046273502","doi":"https://doi.org/10.1109/iccd.2013.6657032","title":"Register allocation and VDD-gating algorithms for out-of-order architectures","display_name":"Register allocation and VDD-gating algorithms for out-of-order architectures","publication_year":2013,"publication_date":"2013-10-01","ids":{"openalex":"https://openalex.org/W2046273502","doi":"https://doi.org/10.1109/iccd.2013.6657032","mag":"2046273502"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.2013.6657032","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2013.6657032","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE 31st International Conference on Computer Design (ICCD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5089050018","display_name":"Steven Battle","orcid":null},"institutions":[{"id":"https://openalex.org/I72816309","display_name":"Drexel University","ror":"https://ror.org/04bdffz58","country_code":"US","type":"education","lineage":["https://openalex.org/I72816309"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Steven J. Battle","raw_affiliation_strings":["Drexel University, Philadelphia, PA, USA","Drexel University, Philadelphia, PA, USA;"],"affiliations":[{"raw_affiliation_string":"Drexel University, Philadelphia, PA, USA","institution_ids":["https://openalex.org/I72816309"]},{"raw_affiliation_string":"Drexel University, Philadelphia, PA, USA;","institution_ids":["https://openalex.org/I72816309"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5018352758","display_name":"Mark Hempstead","orcid":"https://orcid.org/0000-0001-9696-4741"},"institutions":[{"id":"https://openalex.org/I72816309","display_name":"Drexel University","ror":"https://ror.org/04bdffz58","country_code":"US","type":"education","lineage":["https://openalex.org/I72816309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mark Hempstead","raw_affiliation_strings":["Drexel University, Philadelphia, PA, USA","Drexel University, Philadelphia, PA, USA;"],"affiliations":[{"raw_affiliation_string":"Drexel University, Philadelphia, PA, USA","institution_ids":["https://openalex.org/I72816309"]},{"raw_affiliation_string":"Drexel University, Philadelphia, PA, USA;","institution_ids":["https://openalex.org/I72816309"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5089050018"],"corresponding_institution_ids":["https://openalex.org/I72816309"],"apc_list":null,"apc_paid":null,"fwci":0.2365,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.60546023,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"108","last_page":"114"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/power-gating","display_name":"Power gating","score":0.8085114359855652},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6804289817810059},{"id":"https://openalex.org/keywords/gating","display_name":"Gating","score":0.621035099029541},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.5420038104057312},{"id":"https://openalex.org/keywords/radio-frequency","display_name":"Radio frequency","score":0.5387471914291382},{"id":"https://openalex.org/keywords/register-file","display_name":"Register file","score":0.5265624523162842},{"id":"https://openalex.org/keywords/leakage","display_name":"Leakage (economics)","score":0.4373801350593567},{"id":"https://openalex.org/keywords/energy","display_name":"Energy (signal processing)","score":0.41308242082595825},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2926393151283264},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.23431697487831116},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.20378026366233826},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.18341070413589478},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18265220522880554},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.16497090458869934},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.15348300337791443},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.1458127796649933},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.10192427039146423}],"concepts":[{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.8085114359855652},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6804289817810059},{"id":"https://openalex.org/C194544171","wikidata":"https://www.wikidata.org/wiki/Q21105679","display_name":"Gating","level":2,"score":0.621035099029541},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.5420038104057312},{"id":"https://openalex.org/C74064498","wikidata":"https://www.wikidata.org/wiki/Q3396184","display_name":"Radio frequency","level":2,"score":0.5387471914291382},{"id":"https://openalex.org/C117280010","wikidata":"https://www.wikidata.org/wiki/Q180944","display_name":"Register file","level":3,"score":0.5265624523162842},{"id":"https://openalex.org/C2777042071","wikidata":"https://www.wikidata.org/wiki/Q6509304","display_name":"Leakage (economics)","level":2,"score":0.4373801350593567},{"id":"https://openalex.org/C186370098","wikidata":"https://www.wikidata.org/wiki/Q442787","display_name":"Energy (signal processing)","level":2,"score":0.41308242082595825},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2926393151283264},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.23431697487831116},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.20378026366233826},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.18341070413589478},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18265220522880554},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.16497090458869934},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.15348300337791443},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.1458127796649933},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.10192427039146423},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C42407357","wikidata":"https://www.wikidata.org/wiki/Q521","display_name":"Physiology","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccd.2013.6657032","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2013.6657032","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE 31st International Conference on Computer Design (ICCD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.6299999952316284,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W1552317579","https://openalex.org/W1965634199","https://openalex.org/W2005487922","https://openalex.org/W2006312753","https://openalex.org/W2086775835","https://openalex.org/W2089363288","https://openalex.org/W2098335003","https://openalex.org/W2103670614","https://openalex.org/W2112833506","https://openalex.org/W2124976000","https://openalex.org/W2125796904","https://openalex.org/W2126357937","https://openalex.org/W2130870362","https://openalex.org/W2131054871","https://openalex.org/W2158899676","https://openalex.org/W2169137980","https://openalex.org/W2318529517","https://openalex.org/W4235106764","https://openalex.org/W4248310916","https://openalex.org/W4253107871","https://openalex.org/W6633087765","https://openalex.org/W6651700774","https://openalex.org/W6678497183","https://openalex.org/W6830300290"],"related_works":["https://openalex.org/W2259094912","https://openalex.org/W4253895162","https://openalex.org/W4251089459","https://openalex.org/W2090169195","https://openalex.org/W2111412181","https://openalex.org/W2102384429","https://openalex.org/W4250432526","https://openalex.org/W2524541844","https://openalex.org/W2101536355","https://openalex.org/W2518933685"],"abstract_inverted_index":{"Register":[0],"Files":[1],"(RF)":[2],"in":[3,98,105],"modern":[4],"out-of-order":[5],"microprocessors":[6],"can":[7],"account":[8],"for":[9,73,123],"up":[10,134],"to":[11,30,35,92,95,102,110,119,132,135],"30%":[12],"of":[13,24,55,68,137],"total":[14],"power":[15,65],"consumed":[16],"by":[17,82],"the":[18,25,31,46,56,69,99,106,121,127,138],"core.":[19],"The":[20],"complexity":[21],"and":[22,76,86,108,125,146],"size":[23],"RF":[26,47,70],"has":[27],"increased":[28],"due":[29],"transition":[32],"from":[33],"ROB-based":[34],"MIPSR10K-style":[36],"physical":[37,41],"register":[38,74],"renaming.":[39],"Because":[40],"registers":[42,97],"are":[43,80,130],"dynamically":[44],"allocated,":[45],"is":[48],"not":[49],"fully":[50],"occupied":[51],"during":[52],"every":[53],"phase":[54],"application.":[57],"In":[58],"this":[59],"paper,":[60],"we":[61],"propose":[62],"a":[63,142],"comprehensive":[64],"management":[66],"strategy":[67],"through":[71],"algorithms":[72,91],"allocation":[75],"register-bank":[77],"power-gating":[78,126],"that":[79],"informed":[81],"both":[83],"microarchitecture":[84],"details":[85],"circuit":[87,117],"costs.":[88],"We":[89,114,129],"investigate":[90],"control":[93],"where":[94],"place":[96],"RF,":[100,107,145],"when":[101,109],"disable":[103],"banks":[104],"re-enable":[111],"these":[112],"banks.":[113],"include":[115],"detailed":[116],"models":[118],"estimate":[120],"cost":[122],"banking":[124],"RF.":[128],"able":[131],"save":[133,147],"50%":[136],"leakage":[139,150],"energy":[140,151],"vs.":[141],"baseline":[143],"monolithic":[144],"11%":[148],"more":[149],"than":[152],"fine-grained":[153],"VDD-gating":[154],"schemes.":[155]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}