{"id":"https://openalex.org/W2053161625","doi":"https://doi.org/10.1109/iccd.2013.6657029","title":"A private level-1 cache architecture to exploit the latency and capacity tradeoffs in multicores operating at near-threshold voltages","display_name":"A private level-1 cache architecture to exploit the latency and capacity tradeoffs in multicores operating at near-threshold voltages","publication_year":2013,"publication_date":"2013-10-01","ids":{"openalex":"https://openalex.org/W2053161625","doi":"https://doi.org/10.1109/iccd.2013.6657029","mag":"2053161625"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.2013.6657029","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2013.6657029","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE 31st International Conference on Computer Design (ICCD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5043491254","display_name":"Farrukh Hijaz","orcid":"https://orcid.org/0000-0001-9767-2847"},"institutions":[{"id":"https://openalex.org/I140172145","display_name":"University of Connecticut","ror":"https://ror.org/02der9h97","country_code":"US","type":"education","lineage":["https://openalex.org/I140172145"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Farrukh Hijaz","raw_affiliation_strings":["University of Connecticut, Storrs, CT, USA","University of Connecticut, Storrs, CT USA#TAB#"],"affiliations":[{"raw_affiliation_string":"University of Connecticut, Storrs, CT, USA","institution_ids":["https://openalex.org/I140172145"]},{"raw_affiliation_string":"University of Connecticut, Storrs, CT USA#TAB#","institution_ids":["https://openalex.org/I140172145"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077240128","display_name":"Qingchuan Shi","orcid":null},"institutions":[{"id":"https://openalex.org/I140172145","display_name":"University of Connecticut","ror":"https://ror.org/02der9h97","country_code":"US","type":"education","lineage":["https://openalex.org/I140172145"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Qingchuan Shi","raw_affiliation_strings":["University of Connecticut, Storrs, CT, USA","University of Connecticut, Storrs, CT USA#TAB#"],"affiliations":[{"raw_affiliation_string":"University of Connecticut, Storrs, CT, USA","institution_ids":["https://openalex.org/I140172145"]},{"raw_affiliation_string":"University of Connecticut, Storrs, CT USA#TAB#","institution_ids":["https://openalex.org/I140172145"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5048129220","display_name":"Omer Khan","orcid":"https://orcid.org/0000-0001-6293-7403"},"institutions":[{"id":"https://openalex.org/I140172145","display_name":"University of Connecticut","ror":"https://ror.org/02der9h97","country_code":"US","type":"education","lineage":["https://openalex.org/I140172145"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Omer Khan","raw_affiliation_strings":["University of Connecticut, Storrs, CT, USA","University of Connecticut, Storrs, CT USA#TAB#"],"affiliations":[{"raw_affiliation_string":"University of Connecticut, Storrs, CT, USA","institution_ids":["https://openalex.org/I140172145"]},{"raw_affiliation_string":"University of Connecticut, Storrs, CT USA#TAB#","institution_ids":["https://openalex.org/I140172145"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5043491254"],"corresponding_institution_ids":["https://openalex.org/I140172145"],"apc_list":null,"apc_paid":null,"fwci":1.1822,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.81414629,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"85","last_page":"92"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.8486827611923218},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7678501605987549},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.6798810958862305},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.6049116253852844},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.5783365368843079},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.5500506162643433},{"id":"https://openalex.org/keywords/cache-pollution","display_name":"Cache pollution","score":0.5343731045722961},{"id":"https://openalex.org/keywords/smart-cache","display_name":"Smart Cache","score":0.5036296248435974},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.4792916178703308},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.46777263283729553},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.42661386728286743},{"id":"https://openalex.org/keywords/cache-invalidation","display_name":"Cache invalidation","score":0.41342371702194214},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.4132426679134369},{"id":"https://openalex.org/keywords/word-error-rate","display_name":"Word error rate","score":0.4128912091255188},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.38561707735061646},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3060324192047119}],"concepts":[{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.8486827611923218},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7678501605987549},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.6798810958862305},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.6049116253852844},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.5783365368843079},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.5500506162643433},{"id":"https://openalex.org/C113166858","wikidata":"https://www.wikidata.org/wiki/Q5015981","display_name":"Cache pollution","level":5,"score":0.5343731045722961},{"id":"https://openalex.org/C167713795","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"Smart Cache","level":5,"score":0.5036296248435974},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.4792916178703308},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.46777263283729553},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.42661386728286743},{"id":"https://openalex.org/C25536678","wikidata":"https://www.wikidata.org/wiki/Q5015977","display_name":"Cache invalidation","level":5,"score":0.41342371702194214},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.4132426679134369},{"id":"https://openalex.org/C40969351","wikidata":"https://www.wikidata.org/wiki/Q3516228","display_name":"Word error rate","level":2,"score":0.4128912091255188},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.38561707735061646},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3060324192047119},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C28490314","wikidata":"https://www.wikidata.org/wiki/Q189436","display_name":"Speech recognition","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccd.2013.6657029","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2013.6657029","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE 31st International Conference on Computer Design (ICCD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8999999761581421,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":35,"referenced_works":["https://openalex.org/W1972573758","https://openalex.org/W2015800662","https://openalex.org/W2025474944","https://openalex.org/W2031948068","https://openalex.org/W2067168777","https://openalex.org/W2080019739","https://openalex.org/W2101308451","https://openalex.org/W2109824347","https://openalex.org/W2113362353","https://openalex.org/W2114931471","https://openalex.org/W2115150948","https://openalex.org/W2119306084","https://openalex.org/W2126372249","https://openalex.org/W2134682810","https://openalex.org/W2135572164","https://openalex.org/W2136444750","https://openalex.org/W2139342246","https://openalex.org/W2145021036","https://openalex.org/W2146561901","https://openalex.org/W2157447136","https://openalex.org/W2161197576","https://openalex.org/W2161522487","https://openalex.org/W2161648335","https://openalex.org/W2161991038","https://openalex.org/W2168159483","https://openalex.org/W2169875292","https://openalex.org/W2174102096","https://openalex.org/W2916411819","https://openalex.org/W4231535434","https://openalex.org/W4238002809","https://openalex.org/W4238549726","https://openalex.org/W4239788823","https://openalex.org/W4255298641","https://openalex.org/W6673644505","https://openalex.org/W6681884652"],"related_works":["https://openalex.org/W2133489088","https://openalex.org/W2363769136","https://openalex.org/W2114386333","https://openalex.org/W2734782074","https://openalex.org/W2126408955","https://openalex.org/W2098406302","https://openalex.org/W2148571123","https://openalex.org/W2031173804","https://openalex.org/W2115222420","https://openalex.org/W2369103246"],"abstract_inverted_index":{"Near-threshold":[0],"voltage":[1,21],"(NTV)":[2],"operation":[3,17],"is":[4,105,111],"expected":[5,32],"to":[6,9,33,54,81,91,116,134],"enable":[7],"up":[8],"10\u00d7":[10],"energy-efficiency":[11],"for":[12],"future":[13],"processors.":[14],"However,":[15,125],"reliable":[16],"below":[18],"a":[19,95,147,186],"minimum":[20],"(Vccmin)":[22],"cannot":[23],"be":[24,41],"guaranteed.":[25],"Specifically,":[26],"SRAM":[27],"bit-cell":[28,67],"error":[29,68,103,128,207],"rates":[30,208],"are":[31],"rise":[34],"steeply":[35],"since":[36],"their":[37],"margins":[38],"can":[39,73],"easily":[40],"violated":[42],"at":[43,107,126,163,172,203],"near-threshold":[44],"voltages.":[45],"Multicore":[46],"processors":[47],"rely":[48],"on":[49],"fast":[50],"private":[51,149],"L1":[52,71,88,122,150,194],"caches":[53],"exploit":[55],"data":[56],"locality":[57],"and":[58,100,118,156,205],"achieve":[59],"high":[60,66,106,206],"performance.":[61,139],"In":[62],"the":[63,83,120,130,164,177],"presence":[64],"of":[65,166,179,185],"rates,":[69,129],"an":[70],"cache":[72,89,123,136,151,161,195],"either":[74,159],"sacrifice":[75],"capacity":[76,99,137,162,174],"or":[77,170],"incur":[78],"additional":[79,114,121,131,167],"latency":[80,93,115,133,168],"correct":[82],"errors.":[84],"We":[85],"observe":[86],"that":[87,153,191],"sensitivity":[90],"hit":[92,181],"offers":[94],"design":[96],"tradeoff":[97,142],"between":[98],"latency.":[101,182],"When":[102],"rate":[104],"extreme":[108],"Vccmin,":[109],"it":[110],"worthwhile":[112],"incurring":[113],"recover":[117,135],"utilize":[119],"capacity.":[124],"low":[127,204],"constant":[132],"degrades":[138],"With":[140],"this":[141],"in":[143],"mind,":[144],"we":[145,189],"propose":[146],"novel":[148],"architecture":[152,196],"dynamically":[154],"learns":[155],"adapts":[157],"by":[158],"recovering":[160],"cost":[165],"overhead,":[169],"operate":[171],"lower":[173],"while":[175],"utilizing":[176],"benefits":[178],"optimal":[180],"Using":[183],"simulations":[184],"64-core":[187],"multicore,":[188],"demonstrate":[190],"our":[192],"adaptive":[193],"performs":[197],"better":[198],"than":[199],"both":[200],"individual":[201],"schemes":[202],"(i.e.,":[209],"various":[210],"NTV":[211],"conditions).":[212]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
