{"id":"https://openalex.org/W2092757602","doi":"https://doi.org/10.1109/iccd.2012.6378655","title":"Analyzing the optimal ratio of SRAM banks in hybrid caches","display_name":"Analyzing the optimal ratio of SRAM banks in hybrid caches","publication_year":2012,"publication_date":"2012-09-01","ids":{"openalex":"https://openalex.org/W2092757602","doi":"https://doi.org/10.1109/iccd.2012.6378655","mag":"2092757602"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.2012.6378655","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2012.6378655","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE 30th International Conference on Computer Design (ICCD)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5001423758","display_name":"Alejandro Valero","orcid":"https://orcid.org/0000-0002-0824-5833"},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":true,"raw_author_name":"Alejandro Valero","raw_affiliation_strings":["Department of Computer Engineering, Universitat Polit\u00e9cnica de Val\u00e9ncia, Valencia, Spain","Department of Computer Engineering, Universitat Polit\u00e8cnica de Val\u00e8ncia, Valencia, Spain#TAB#"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Universitat Polit\u00e9cnica de Val\u00e9ncia, Valencia, Spain","institution_ids":["https://openalex.org/I60053951"]},{"raw_affiliation_string":"Department of Computer Engineering, Universitat Polit\u00e8cnica de Val\u00e8ncia, Valencia, Spain#TAB#","institution_ids":["https://openalex.org/I60053951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044390347","display_name":"Julio Sahuquillo","orcid":"https://orcid.org/0000-0001-8630-4846"},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Julio Sahuquillo","raw_affiliation_strings":["Department of Computer Engineering, Universitat Polit\u00e9cnica de Val\u00e9ncia, Valencia, Spain","Department of Computer Engineering, Universitat Polit\u00e8cnica de Val\u00e8ncia, Valencia, Spain#TAB#"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Universitat Polit\u00e9cnica de Val\u00e9ncia, Valencia, Spain","institution_ids":["https://openalex.org/I60053951"]},{"raw_affiliation_string":"Department of Computer Engineering, Universitat Polit\u00e8cnica de Val\u00e8ncia, Valencia, Spain#TAB#","institution_ids":["https://openalex.org/I60053951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013237315","display_name":"Salvador Petit","orcid":"https://orcid.org/0000-0003-2426-4134"},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Salvador Petit","raw_affiliation_strings":["Department of Computer Engineering, Universitat Polit\u00e9cnica de Val\u00e9ncia, Valencia, Spain","Department of Computer Engineering, Universitat Polit\u00e8cnica de Val\u00e8ncia, Valencia, Spain#TAB#"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Universitat Polit\u00e9cnica de Val\u00e9ncia, Valencia, Spain","institution_ids":["https://openalex.org/I60053951"]},{"raw_affiliation_string":"Department of Computer Engineering, Universitat Polit\u00e8cnica de Val\u00e8ncia, Valencia, Spain#TAB#","institution_ids":["https://openalex.org/I60053951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101612028","display_name":"Pedro L\u00f3pez","orcid":"https://orcid.org/0000-0003-4544-955X"},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Pedro Lopez","raw_affiliation_strings":["Department of Computer Engineering, Universitat Polit\u00e9cnica de Val\u00e9ncia, Valencia, Spain","Department of Computer Engineering, Universitat Polit\u00e8cnica de Val\u00e8ncia, Valencia, Spain#TAB#"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Universitat Polit\u00e9cnica de Val\u00e9ncia, Valencia, Spain","institution_ids":["https://openalex.org/I60053951"]},{"raw_affiliation_string":"Department of Computer Engineering, Universitat Polit\u00e8cnica de Val\u00e8ncia, Valencia, Spain#TAB#","institution_ids":["https://openalex.org/I60053951"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5040384183","display_name":"J. Duato","orcid":"https://orcid.org/0000-0002-7785-0607"},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Jose Duato","raw_affiliation_strings":["Department of Computer Engineering, Universitat Polit\u00e9cnica de Val\u00e9ncia, Valencia, Spain","Department of Computer Engineering, Universitat Polit\u00e8cnica de Val\u00e8ncia, Valencia, Spain#TAB#"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Universitat Polit\u00e9cnica de Val\u00e9ncia, Valencia, Spain","institution_ids":["https://openalex.org/I60053951"]},{"raw_affiliation_string":"Department of Computer Engineering, Universitat Polit\u00e8cnica de Val\u00e8ncia, Valencia, Spain#TAB#","institution_ids":["https://openalex.org/I60053951"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5001423758"],"corresponding_institution_ids":["https://openalex.org/I60053951"],"apc_list":null,"apc_paid":null,"fwci":1.4503,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.82124789,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"25","issue":null,"first_page":"297","last_page":"302"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.8919379711151123},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.7897579669952393},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5856351256370544},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.5224744081497192},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5080826282501221},{"id":"https://openalex.org/keywords/universal-memory","display_name":"Universal memory","score":0.4964674115180969},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.41255396604537964},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.31951814889907837},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.26719075441360474},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1948784589767456},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.1725752055644989},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.16042202711105347},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.09808266162872314}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.8919379711151123},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.7897579669952393},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5856351256370544},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.5224744081497192},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5080826282501221},{"id":"https://openalex.org/C195053848","wikidata":"https://www.wikidata.org/wiki/Q7894141","display_name":"Universal memory","level":5,"score":0.4964674115180969},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.41255396604537964},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.31951814889907837},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.26719075441360474},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1948784589767456},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.1725752055644989},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.16042202711105347},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.09808266162872314},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccd.2012.6378655","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2012.6378655","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE 30th International Conference on Computer Design (ICCD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8999999761581421}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1965522623","https://openalex.org/W1967626924","https://openalex.org/W1980364632","https://openalex.org/W2023062763","https://openalex.org/W2032094184","https://openalex.org/W2038061869","https://openalex.org/W2064037464","https://openalex.org/W2064977311","https://openalex.org/W2074113453","https://openalex.org/W2076264849","https://openalex.org/W2090662896","https://openalex.org/W2114429886","https://openalex.org/W2144308571","https://openalex.org/W2159253302","https://openalex.org/W2323110450","https://openalex.org/W2916411819","https://openalex.org/W3147067924","https://openalex.org/W6656149995"],"related_works":["https://openalex.org/W1974599144","https://openalex.org/W4384572207","https://openalex.org/W370196896","https://openalex.org/W2980976157","https://openalex.org/W2188908293","https://openalex.org/W4312284151","https://openalex.org/W2091411788","https://openalex.org/W2793465010","https://openalex.org/W3205888584","https://openalex.org/W4241706897"],"abstract_inverted_index":{"Cache":[0],"memories":[1],"have":[2,122],"been":[3,123],"typically":[4],"implemented":[5],"with":[6,42,48,154,168,173],"Static":[7],"Random":[8],"Access":[9],"Memory":[10],"(SRAM)":[11],"technology.":[12],"This":[13,79],"technology":[14,36,55,192],"presents":[15],"a":[16,49,82,150,186,190,200,204,222,233],"fast":[17,133],"access":[18,51],"time":[19],"but":[20],"high":[21,182],"energy":[22,44],"consumption":[23],"and":[24,45,59,89,99,111,218],"low":[25],"density.":[26],"As":[27],"opposite,":[28],"the":[29,72,94,106,116,127,155,194,208,213,227,239],"recently":[30],"appeared":[31],"embedded":[32],"Dynamic":[33],"RAM":[34],"(eDRAM)":[35],"allows":[37],"caches":[38],"to":[39,92,125,139,149],"be":[40,180],"built":[41,172],"lower":[43],"area,":[46],"although":[47],"slower":[50],"time.":[52],"The":[53],"eDRAM":[54,90,112,216,224],"provides":[56],"important":[57],"leakage":[58],"area":[60,74,177],"savings,":[61],"especially":[62],"in":[63,75,132],"huge":[64],"Last-Level":[65],"Caches":[66],"(LLCs),":[67],"which":[68,86],"occupy":[69],"almost":[70],"half":[71],"silicon":[73],"some":[76],"recent":[77],"microprocessors.":[78],"paper":[80],"proposes":[81],"novel":[83],"hybrid":[84,201],"LLC,":[85],"combines":[87],"SRAM":[88,110,134,152,174,210,230],"banks":[91,113,135,171,231],"address":[93],"trade-off":[95],"among":[96],"performance,":[97],"energy,":[98],"area.":[100],"To":[101],"this":[102],"end,":[103],"we":[104],"explore":[105],"optimal":[107],"percentage":[108],"of":[109,170,215,229,238],"that":[114,199],"achieves":[115],"best":[117],"target":[118],"trade-off.":[119],"Architectural":[120],"mechanisms":[121],"devised":[124],"keep":[126],"most":[128],"likely":[129],"accessed":[130],"blocks":[131],"as":[136,138,181,183],"well":[137],"avoid":[140],"unnecessary":[141],"destructive":[142],"reads.":[143],"Experimental":[144],"results":[145],"show":[146],"that,":[147],"compared":[148],"conventional":[151,209,223],"LLC":[153],"same":[156],"storage":[157],"capacity,":[158],"performance":[159],"degradation":[160],"does":[161],"not":[162],"surpass,":[163],"on":[164],"average,":[165],"2.9%":[166],"(even":[167],"12.5%":[169],"technology),":[175],"whereas":[176],"savings":[178],"can":[179],"46%":[184],"for":[185],"1MB-16way":[187],"LLC.":[188],"For":[189],"45nm":[191],"node,":[193],"energy-delay":[195],"squared":[196],"product":[197],"confirms":[198],"cache":[202,211,225,240],"is":[203,232],"better":[205,220],"design":[206],"than":[207,221],"regardless":[212],"number":[214,228],"banks,":[217],"also":[219],"when":[226],"quarter":[234],"or":[235],"an":[236],"eighth":[237],"banks.":[241]},"counts_by_year":[{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
