{"id":"https://openalex.org/W2053036251","doi":"https://doi.org/10.1109/iccd.2011.6081429","title":"CPACT - The conditional parameter adjustment cache tuner for dual-core architectures","display_name":"CPACT - The conditional parameter adjustment cache tuner for dual-core architectures","publication_year":2011,"publication_date":"2011-10-01","ids":{"openalex":"https://openalex.org/W2053036251","doi":"https://doi.org/10.1109/iccd.2011.6081429","mag":"2053036251"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.2011.6081429","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2011.6081429","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE 29th International Conference on Computer Design (ICCD)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5060374059","display_name":"Marisha Rawlins","orcid":null},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Marisha Rawlins","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA","Department of Electrical and Computer Engineering, University of Florida, Gainesville, 32611, USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA","institution_ids":["https://openalex.org/I33213144"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Florida, Gainesville, 32611, USA#TAB#","institution_ids":["https://openalex.org/I33213144"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5035415168","display_name":"Ann Gordon-Ross","orcid":"https://orcid.org/0000-0001-8865-8381"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ann Gordon-Ross","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA","Department of Electrical and Computer Engineering, University of Florida, Gainesville, 32611, USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA","institution_ids":["https://openalex.org/I33213144"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Florida, Gainesville, 32611, USA#TAB#","institution_ids":["https://openalex.org/I33213144"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I33213144"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"396","last_page":"403"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.8219813108444214},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8075292706489563},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.6137019395828247},{"id":"https://openalex.org/keywords/smart-cache","display_name":"Smart Cache","score":0.5956377387046814},{"id":"https://openalex.org/keywords/cache-invalidation","display_name":"Cache invalidation","score":0.5875978469848633},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5841215252876282},{"id":"https://openalex.org/keywords/cache-pollution","display_name":"Cache pollution","score":0.5587039589881897},{"id":"https://openalex.org/keywords/mesi-protocol","display_name":"MESI protocol","score":0.48352861404418945},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.4754495322704315},{"id":"https://openalex.org/keywords/core","display_name":"Core (optical fiber)","score":0.45752015709877014},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.4372168183326721},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.36363720893859863}],"concepts":[{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.8219813108444214},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8075292706489563},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.6137019395828247},{"id":"https://openalex.org/C167713795","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"Smart Cache","level":5,"score":0.5956377387046814},{"id":"https://openalex.org/C25536678","wikidata":"https://www.wikidata.org/wiki/Q5015977","display_name":"Cache invalidation","level":5,"score":0.5875978469848633},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5841215252876282},{"id":"https://openalex.org/C113166858","wikidata":"https://www.wikidata.org/wiki/Q5015981","display_name":"Cache pollution","level":5,"score":0.5587039589881897},{"id":"https://openalex.org/C120936851","wikidata":"https://www.wikidata.org/wiki/Q1408065","display_name":"MESI protocol","level":5,"score":0.48352861404418945},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.4754495322704315},{"id":"https://openalex.org/C2164484","wikidata":"https://www.wikidata.org/wiki/Q5170150","display_name":"Core (optical fiber)","level":2,"score":0.45752015709877014},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.4372168183326721},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.36363720893859863},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccd.2011.6081429","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2011.6081429","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE 29th International Conference on Computer Design (ICCD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8999999761581421}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":39,"referenced_works":["https://openalex.org/W1624489350","https://openalex.org/W1943109230","https://openalex.org/W1967474856","https://openalex.org/W1980419087","https://openalex.org/W2049964141","https://openalex.org/W2070553643","https://openalex.org/W2093036945","https://openalex.org/W2098030829","https://openalex.org/W2099708455","https://openalex.org/W2110500672","https://openalex.org/W2117102169","https://openalex.org/W2123889672","https://openalex.org/W2128419576","https://openalex.org/W2131507936","https://openalex.org/W2132366470","https://openalex.org/W2135695139","https://openalex.org/W2141103990","https://openalex.org/W2145021036","https://openalex.org/W2147943147","https://openalex.org/W2155168119","https://openalex.org/W2155828618","https://openalex.org/W2156252747","https://openalex.org/W2162415743","https://openalex.org/W2170806963","https://openalex.org/W2243416539","https://openalex.org/W2464177207","https://openalex.org/W2545380179","https://openalex.org/W3144074121","https://openalex.org/W4234144196","https://openalex.org/W4238549726","https://openalex.org/W4245448408","https://openalex.org/W4247264372","https://openalex.org/W4256470818","https://openalex.org/W6678452623","https://openalex.org/W6681580856","https://openalex.org/W6683256541","https://openalex.org/W6685012072","https://openalex.org/W6719768283","https://openalex.org/W6729031703"],"related_works":["https://openalex.org/W4312759433","https://openalex.org/W273173017","https://openalex.org/W1521238853","https://openalex.org/W2801630946","https://openalex.org/W2184371594","https://openalex.org/W2135365633","https://openalex.org/W2152423944","https://openalex.org/W2290179447","https://openalex.org/W1652973653","https://openalex.org/W1988497841"],"abstract_inverted_index":{"Cache":[0],"tuning":[1,28,49,71,104],"reveals":[2],"substantial":[3],"energy":[4,57],"savings":[5],"for":[6,15],"single-core":[7,63],"architectures,":[8],"but":[9],"has":[10],"yet":[11],"to":[12,62],"be":[13],"explored":[14],"multi-core":[16],"architectures.":[17],"In":[18],"this":[19],"paper":[20],"we":[21,93],"explore":[22],"level":[23],"one":[24],"(L1)":[25],"data":[26,36,47,64,100],"cache":[27,37,48,65,76],"in":[29,50],"a":[30,40,51],"heterogeneous":[31],"dual-core":[32,52,70],"system":[33,53],"where":[34],"each":[35],"can":[38],"have":[39],"different":[41],"configuration.":[42],"We":[43,67],"show":[44],"that":[45],"L1":[46],"achieves":[54],"25%":[55],"average":[56],"savings,":[58],"which":[59,74],"is":[60],"comparable":[61],"tuning.":[66],"present":[68],"the":[69,81,89,105],"heuristic":[72],"CPACT,":[73],"finds":[75],"configurations":[77],"within":[78],"1%":[79,87],"of":[80,88],"optimal":[82],"configuration":[83],"while":[84],"searching":[85],"only":[86],"design":[90],"space.":[91],"Finally,":[92],"provide":[94],"valuable":[95],"insights":[96],"on":[97],"core-interactions":[98],"and":[99],"coherence":[101],"revealed":[102],"when":[103],"multithreaded":[106],"SPLASH-2":[107],"benchmarks.":[108]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":6}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
