{"id":"https://openalex.org/W2026369926","doi":"https://doi.org/10.1109/iccd.2011.6081409","title":"Impact and optimization of lithography-aware regular layout in digital circuit design","display_name":"Impact and optimization of lithography-aware regular layout in digital circuit design","publication_year":2011,"publication_date":"2011-10-01","ids":{"openalex":"https://openalex.org/W2026369926","doi":"https://doi.org/10.1109/iccd.2011.6081409","mag":"2026369926"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.2011.6081409","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2011.6081409","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE 29th International Conference on Computer Design (ICCD)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5069159349","display_name":"Vin\u00edcius Dal","orcid":null},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Vinicius Dal Bem","raw_affiliation_strings":["Graduate Program in Microelectronics (PGMicro), Federal University of Rio Grande do Sul, Porto Alegre, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate Program in Microelectronics (PGMicro), Federal University of Rio Grande do Sul, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062131940","display_name":"Paulo F. Butzen","orcid":"https://orcid.org/0000-0003-1587-7596"},"institutions":[{"id":"https://openalex.org/I126460647","display_name":"Universidade Federal do Rio Grande","ror":"https://ror.org/05hpfkn88","country_code":"BR","type":"education","lineage":["https://openalex.org/I126460647"]},{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Paulo Butzen","raw_affiliation_strings":["Center of Computational Science, Federal University of Rio Grande, Rio Grande, Brazil","Graduate Program in Microelectronics (PGMicro), Federal University of Rio Grande do Sul, Porto Alegre, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Center of Computational Science, Federal University of Rio Grande, Rio Grande, Brazil","institution_ids":["https://openalex.org/I126460647"]},{"raw_affiliation_string":"Graduate Program in Microelectronics (PGMicro), Federal University of Rio Grande do Sul, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010444815","display_name":"Felipe S. Marranghello","orcid":"https://orcid.org/0000-0002-5368-6750"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Felipe S. Marranghello","raw_affiliation_strings":["Graduate Program in Microelectronics (PGMicro), Federal University of Rio Grande do Sul, Porto Alegre, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate Program in Microelectronics (PGMicro), Federal University of Rio Grande do Sul, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065397615","display_name":"Andr\u00e9 I. Reis","orcid":"https://orcid.org/0000-0002-3118-8160"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Andre I. Reis","raw_affiliation_strings":["Graduate Program in Microelectronics (PGMicro), Federal University of Rio Grande do Sul, Porto Alegre, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate Program in Microelectronics (PGMicro), Federal University of Rio Grande do Sul, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5090563366","display_name":"Renato P. Ribas","orcid":"https://orcid.org/0000-0002-9895-7489"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Renato P. Ribas","raw_affiliation_strings":["Graduate Program in Microelectronics (PGMicro), Federal University of Rio Grande do Sul, Porto Alegre, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate Program in Microelectronics (PGMicro), Federal University of Rio Grande do Sul, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"22","issue":null,"first_page":"279","last_page":"284"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.6182806491851807},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.5845004916191101},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5710951089859009},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5635855793952942},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.5410628914833069},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.520308256149292},{"id":"https://openalex.org/keywords/lithography","display_name":"Lithography","score":0.5150046348571777},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.4961629807949066},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.47110798954963684},{"id":"https://openalex.org/keywords/ic-layout-editor","display_name":"IC layout editor","score":0.43462440371513367},{"id":"https://openalex.org/keywords/design-layout-record","display_name":"Design layout record","score":0.4275299906730652},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4260174632072449},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.4099477231502533},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.39563414454460144},{"id":"https://openalex.org/keywords/circuit-extraction","display_name":"Circuit extraction","score":0.35789158940315247},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.32729023694992065},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2327277660369873},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.21801847219467163},{"id":"https://openalex.org/keywords/equivalent-circuit","display_name":"Equivalent circuit","score":0.14949840307235718},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.14632928371429443},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.1234714686870575}],"concepts":[{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.6182806491851807},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.5845004916191101},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5710951089859009},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5635855793952942},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.5410628914833069},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.520308256149292},{"id":"https://openalex.org/C204223013","wikidata":"https://www.wikidata.org/wiki/Q133036","display_name":"Lithography","level":2,"score":0.5150046348571777},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.4961629807949066},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.47110798954963684},{"id":"https://openalex.org/C5546195","wikidata":"https://www.wikidata.org/wiki/Q5969842","display_name":"IC layout editor","level":5,"score":0.43462440371513367},{"id":"https://openalex.org/C179145894","wikidata":"https://www.wikidata.org/wiki/Q5264353","display_name":"Design layout record","level":5,"score":0.4275299906730652},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4260174632072449},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.4099477231502533},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.39563414454460144},{"id":"https://openalex.org/C26490066","wikidata":"https://www.wikidata.org/wiki/Q17006835","display_name":"Circuit extraction","level":4,"score":0.35789158940315247},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.32729023694992065},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2327277660369873},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.21801847219467163},{"id":"https://openalex.org/C23572009","wikidata":"https://www.wikidata.org/wiki/Q964981","display_name":"Equivalent circuit","level":3,"score":0.14949840307235718},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.14632928371429443},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.1234714686870575},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccd.2011.6081409","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2011.6081409","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE 29th International Conference on Computer Design (ICCD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.4000000059604645}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W1492192095","https://openalex.org/W1503082651","https://openalex.org/W1511688816","https://openalex.org/W1594489858","https://openalex.org/W1965232212","https://openalex.org/W1978155484","https://openalex.org/W1987067207","https://openalex.org/W2053913299","https://openalex.org/W2063553865","https://openalex.org/W2100344939","https://openalex.org/W2109887272","https://openalex.org/W2124007645","https://openalex.org/W2134697552","https://openalex.org/W2136529576","https://openalex.org/W2141429499","https://openalex.org/W2142024736","https://openalex.org/W2157128002","https://openalex.org/W2162002393","https://openalex.org/W2164012847","https://openalex.org/W4230970194","https://openalex.org/W4248303983","https://openalex.org/W6630623413","https://openalex.org/W6682909919"],"related_works":["https://openalex.org/W2091329789","https://openalex.org/W1605062719","https://openalex.org/W2376028644","https://openalex.org/W2357425846","https://openalex.org/W162881505","https://openalex.org/W2044122268","https://openalex.org/W2162651506","https://openalex.org/W2376726667","https://openalex.org/W583900352","https://openalex.org/W1965232212"],"abstract_inverted_index":{"Regular":[0],"fabrics":[1],"are":[2],"expected":[3],"to":[4,65,74],"mitigate":[5],"manufacturing":[6],"process":[7],"variations,":[8],"increasing":[9],"fabrication":[10],"yield":[11],"in":[12,26],"deep":[13],"sub-micron":[14],"CMOS":[15],"technologies.":[16],"This":[17,78],"paper":[18,79],"presents":[19],"an":[20],"extensive":[21],"analysis":[22],"of":[23,29,36],"aspects":[24],"involved":[25],"the":[27,37,46,57,81,111,120],"optimization":[28,60],"regular":[30,40,75,86,96],"fabric":[31,41,58,121],"(based)":[32],"designs.":[33],"The":[34],"choice":[35],"most":[38],"efficient":[39],"design":[42,76,112],"strategy":[43],"depends":[44],"on":[45],"area":[47,69],"overhead":[48],"and":[49,70],"circuit":[50],"performance":[51,71],"degradation,":[52],"which":[53],"may":[54],"vary":[55],"according":[56],"pattern":[59,122],"possibilities.":[61],"Yield":[62],"improvements":[63],"have":[64,91,108],"be":[66],"traded-off":[67],"against":[68],"losses":[72,82],"due":[73],"rules.":[77],"evaluates":[80],"introduced":[83],"by":[84,117],"using":[85],"fabrics.":[87],"Several":[88],"benchmark":[89],"circuits":[90],"been":[92],"mapped":[93],"over":[94],"different":[95],"layout":[97],"templates":[98],"through":[99],"specific":[100],"cell":[101],"libraries":[102],"built":[103],"for":[104],"this":[105],"purpose.":[106],"Results":[107],"demonstrated":[109],"that":[110],"impact":[113],"is":[114],"quite":[115],"manageable":[116],"choosing":[118],"appropriately":[119],"or":[123],"template.":[124]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
