{"id":"https://openalex.org/W1997922946","doi":"https://doi.org/10.1109/iccd.2011.6081397","title":"A queueing theoretic approach for performance evaluation of low-power multi-core embedded systems","display_name":"A queueing theoretic approach for performance evaluation of low-power multi-core embedded systems","publication_year":2011,"publication_date":"2011-10-01","ids":{"openalex":"https://openalex.org/W1997922946","doi":"https://doi.org/10.1109/iccd.2011.6081397","mag":"1997922946"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.2011.6081397","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2011.6081397","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE 29th International Conference on Computer Design (ICCD)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5024203425","display_name":"Arslan Munir","orcid":"https://orcid.org/0000-0002-3126-8945"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Arslan Munir","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA","Dept. of Electrical and Computer Engineering, Univ. of Florida, Gainesville, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA","institution_ids":["https://openalex.org/I33213144"]},{"raw_affiliation_string":"Dept. of Electrical and Computer Engineering, Univ. of Florida, Gainesville, USA","institution_ids":["https://openalex.org/I33213144"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102928781","display_name":"Ross Gordon","orcid":"https://orcid.org/0000-0003-1034-8695"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ann Gordon-Ross","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA","Dept. of Electrical and Computer Engineering, Univ. of Florida, Gainesville, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA","institution_ids":["https://openalex.org/I33213144"]},{"raw_affiliation_string":"Dept. of Electrical and Computer Engineering, Univ. of Florida, Gainesville, USA","institution_ids":["https://openalex.org/I33213144"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5077570468","display_name":"Sanjay Ranka","orcid":"https://orcid.org/0000-0003-4886-1988"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sanjay Ranka","raw_affiliation_strings":["Department of Computer and Information Science and Engineering, University of Florida, Gainesville, FL, USA","Dept. of Computer & Information Science & Engineering, University of Florida, Gainesville, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer and Information Science and Engineering, University of Florida, Gainesville, FL, USA","institution_ids":["https://openalex.org/I33213144"]},{"raw_affiliation_string":"Dept. of Computer & Information Science & Engineering, University of Florida, Gainesville, USA","institution_ids":["https://openalex.org/I33213144"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I33213144"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"11","issue":null,"first_page":"198","last_page":"205"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10772","display_name":"Distributed systems and fault tolerance","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7935785055160522},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5982200503349304},{"id":"https://openalex.org/keywords/expediting","display_name":"Expediting","score":0.5834416151046753},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.5331066846847534},{"id":"https://openalex.org/keywords/queueing-theory","display_name":"Queueing theory","score":0.5151902437210083},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5036868453025818},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.4133298397064209},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.395170658826828},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3372378647327423},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.15746262669563293}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7935785055160522},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5982200503349304},{"id":"https://openalex.org/C134448949","wikidata":"https://www.wikidata.org/wiki/Q1384274","display_name":"Expediting","level":2,"score":0.5834416151046753},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.5331066846847534},{"id":"https://openalex.org/C22684755","wikidata":"https://www.wikidata.org/wiki/Q847526","display_name":"Queueing theory","level":2,"score":0.5151902437210083},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5036868453025818},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.4133298397064209},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.395170658826828},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3372378647327423},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.15746262669563293},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccd.2011.6081397","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2011.6081397","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE 29th International Conference on Computer Design (ICCD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.4300000071525574,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320334593","display_name":"Natural Sciences and Engineering Research Council of Canada","ror":"https://ror.org/01h531d29"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":35,"referenced_works":["https://openalex.org/W159719520","https://openalex.org/W1523829231","https://openalex.org/W1556885469","https://openalex.org/W1591870472","https://openalex.org/W1842183679","https://openalex.org/W1850405760","https://openalex.org/W1964232008","https://openalex.org/W1973602358","https://openalex.org/W1978006658","https://openalex.org/W1985856855","https://openalex.org/W2040901681","https://openalex.org/W2041997506","https://openalex.org/W2048118645","https://openalex.org/W2050487400","https://openalex.org/W2068564784","https://openalex.org/W2070215238","https://openalex.org/W2071006253","https://openalex.org/W2085237598","https://openalex.org/W2085385727","https://openalex.org/W2092627171","https://openalex.org/W2106270437","https://openalex.org/W2114386333","https://openalex.org/W2140130374","https://openalex.org/W2143749395","https://openalex.org/W2145021036","https://openalex.org/W2150465792","https://openalex.org/W2155396321","https://openalex.org/W2157070686","https://openalex.org/W2158924248","https://openalex.org/W2167938142","https://openalex.org/W4300858476","https://openalex.org/W6660844587","https://openalex.org/W6684853892","https://openalex.org/W6996654353","https://openalex.org/W7052928840"],"related_works":["https://openalex.org/W2085395339","https://openalex.org/W2024632604","https://openalex.org/W2071999521","https://openalex.org/W2068005943","https://openalex.org/W2010478499","https://openalex.org/W4317792299","https://openalex.org/W2050011582","https://openalex.org/W2071715249","https://openalex.org/W2051220639","https://openalex.org/W2091881573"],"abstract_inverted_index":{"With":[0],"Moore's":[1],"law":[2],"supplying":[3],"billions":[4],"of":[5,31,62,74,113,122,148,159,165,215,227],"transistors":[6],"on-chip,":[7],"embedded":[8,63,75,100,142,161,179],"systems":[9,64,76,101],"are":[10],"undergoing":[11],"a":[12,54,93,104,145,156,213],"transition":[13],"from":[14],"single-core":[15],"to":[16,18,44,77,85,119,154],"multi-core":[17,99,123,141,178],"exploit":[19],"this":[20,66,89],"high":[21,25,206],"transistor":[22],"density":[23],"for":[24,97,139,205],"performance.":[26],"However,":[27],"the":[28,37,71,79,120,189,225],"optimal":[29],"layout":[30],"these":[32,129],"multiple":[33],"cores":[34,150],"along":[35],"with":[36,144],"memory":[38,199,222],"subsystem":[39],"(caches":[40],"and":[41,48,69,106,115,125,136,151,168,173,202,217],"main":[42,198,221],"memory)":[43],"satisfy":[45],"power,":[46],"area,":[47,167],"often":[49],"stringent":[50],"real-time":[51],"constraints":[52],"is":[53],"challenging":[55],"design":[56,67],"endeavor.":[57],"The":[58],"short":[59],"time-to-market":[60,80],"constraint":[61],"exacerbates":[65],"challenge":[68],"necessitates":[70],"architectural":[72],"modeling":[73,98],"reduce":[78],"by":[81],"expediting":[82],"target":[83],"applications":[84],"device/architecture":[86],"mapping.":[87],"In":[88],"paper,":[90],"we":[91],"present":[92],"queueing":[94],"theoretic":[95],"approach":[96],"that":[102,177,182],"provides":[103],"quick":[105],"inexpensive":[107],"performance":[108,172,192,229],"evaluation":[109],"both":[110],"in":[111,163],"terms":[112,164],"time":[114,201],"resources":[116],"as":[117],"compared":[118],"development":[121],"simulators":[124],"running":[126],"benchmarks":[127],"on":[128],"simulators.":[130],"We":[131],"also":[132],"calculate":[133],"chip":[134],"area":[135],"power":[137,169,174],"consumption":[138],"different":[140],"architectures":[143,162,181,211],"varying":[146],"number":[147],"processor":[149],"cache":[152,207],"configurations":[153],"provide":[155,188],"comparative":[157],"analysis":[158],"multicore":[160],"performance,":[166],"consumption.":[170],"Our":[171],"results":[175],"indicate":[176],"system":[180],"leverage":[183],"shared":[184,218],"last-level":[185],"caches":[186],"(LLCs)":[187],"best":[190],"LLC":[191],"per":[193,230],"watt":[194],"but":[195],"may":[196],"introduce":[197],"response":[200],"throughput":[203],"bottlenecks":[204,223],"miss":[208],"rates,":[209],"whereas":[210],"leveraging":[212],"hybrid":[214],"private":[216],"LLCs":[219],"alleviate":[220],"at":[224],"expense":[226],"reduced":[228],"watt.":[231]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2015,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}