{"id":"https://openalex.org/W2041532085","doi":"https://doi.org/10.1109/iccd.2010.5647784","title":"Routability-driven flip-flop merging process for clock power reduction","display_name":"Routability-driven flip-flop merging process for clock power reduction","publication_year":2010,"publication_date":"2010-10-01","ids":{"openalex":"https://openalex.org/W2041532085","doi":"https://doi.org/10.1109/iccd.2010.5647784","mag":"2041532085"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.2010.5647784","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2010.5647784","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 IEEE International Conference on Computer Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100442705","display_name":"Zhiwei Chen","orcid":"https://orcid.org/0000-0002-2152-815X"},"institutions":[{"id":"https://openalex.org/I59460038","display_name":"Chung Hua University","ror":"https://ror.org/01yzz0f51","country_code":"TW","type":"education","lineage":["https://openalex.org/I59460038"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Zhi-Wei Chen","raw_affiliation_strings":["College of Engineering, Chung Hua University, Hsinchu, Taiwan","College of Engineering Chung-Hua University, Hsinchu, Taiwan, R.O.C"],"affiliations":[{"raw_affiliation_string":"College of Engineering, Chung Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I59460038"]},{"raw_affiliation_string":"College of Engineering Chung-Hua University, Hsinchu, Taiwan, R.O.C","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5071940138","display_name":"Jin-Tai Yan","orcid":"https://orcid.org/0000-0002-7614-2545"},"institutions":[{"id":"https://openalex.org/I59460038","display_name":"Chung Hua University","ror":"https://ror.org/01yzz0f51","country_code":"TW","type":"education","lineage":["https://openalex.org/I59460038"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Jin-Tai Yan","raw_affiliation_strings":["Department of Computer Science and Information Engineering, Chung Hua University, Hsinchu, Taiwan","Department of Computer Science and Information Engineering, Chung-Hua University, Hsinchu, Taiwan, R. O. C"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Information Engineering, Chung Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I59460038"]},{"raw_affiliation_string":"Department of Computer Science and Information Engineering, Chung-Hua University, Hsinchu, Taiwan, R. O. C","institution_ids":["https://openalex.org/I59460038"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5100442705"],"corresponding_institution_ids":["https://openalex.org/I59460038"],"apc_list":null,"apc_paid":null,"fwci":2.0205,"has_fulltext":false,"cited_by_count":24,"citation_normalized_percentile":{"value":0.87281744,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"203","last_page":"208"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9968000054359436,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/flip-flop","display_name":"Flip-flop","score":0.7507897615432739},{"id":"https://openalex.org/keywords/flops","display_name":"FLOPS","score":0.6342283487319946},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.589909017086029},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5819187760353088},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4590619206428528},{"id":"https://openalex.org/keywords/bin","display_name":"Bin","score":0.4580684006214142},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.45228904485702515},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4398239552974701},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.41146278381347656},{"id":"https://openalex.org/keywords/merge","display_name":"Merge (version control)","score":0.4112076163291931},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3837364912033081},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3137814998626709},{"id":"https://openalex.org/keywords/enhanced-data-rates-for-gsm-evolution","display_name":"Enhanced Data Rates for GSM Evolution","score":0.2935523986816406},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.25954607129096985},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2495633363723755},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1542789340019226},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07994109392166138}],"concepts":[{"id":"https://openalex.org/C2781007278","wikidata":"https://www.wikidata.org/wiki/Q183406","display_name":"Flip-flop","level":3,"score":0.7507897615432739},{"id":"https://openalex.org/C3826847","wikidata":"https://www.wikidata.org/wiki/Q188768","display_name":"FLOPS","level":2,"score":0.6342283487319946},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.589909017086029},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5819187760353088},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4590619206428528},{"id":"https://openalex.org/C156273044","wikidata":"https://www.wikidata.org/wiki/Q4913766","display_name":"Bin","level":2,"score":0.4580684006214142},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.45228904485702515},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4398239552974701},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.41146278381347656},{"id":"https://openalex.org/C197129107","wikidata":"https://www.wikidata.org/wiki/Q1921621","display_name":"Merge (version control)","level":2,"score":0.4112076163291931},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3837364912033081},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3137814998626709},{"id":"https://openalex.org/C162307627","wikidata":"https://www.wikidata.org/wiki/Q204833","display_name":"Enhanced Data Rates for GSM Evolution","level":2,"score":0.2935523986816406},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.25954607129096985},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2495633363723755},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1542789340019226},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07994109392166138},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccd.2010.5647784","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2010.5647784","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 IEEE International Conference on Computer Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8700000047683716}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1606273061","https://openalex.org/W2099190567","https://openalex.org/W2145964793","https://openalex.org/W2156849124","https://openalex.org/W2162211138","https://openalex.org/W2243873823","https://openalex.org/W4240722455","https://openalex.org/W4285719527","https://openalex.org/W6675008304","https://openalex.org/W6690558475"],"related_works":["https://openalex.org/W2262031297","https://openalex.org/W2024069812","https://openalex.org/W2025474644","https://openalex.org/W2733322820","https://openalex.org/W2056378213","https://openalex.org/W2482318635","https://openalex.org/W2045056374","https://openalex.org/W2298981088","https://openalex.org/W2163601309","https://openalex.org/W2350494013"],"abstract_inverted_index":{"The":[0,99],"concept":[1],"of":[2,52,109,121],"merging":[3,44],"some":[4,92],"1-bit":[5,53,89],"flip-flops":[6,54,90,94],"into":[7,91],"a":[8,25,50,78],"multi-bit":[9,93],"flip-flop":[10,22,111],"is":[11,85],"applied":[12],"to":[13,37,87,113],"reduce":[14],"dynamic":[15],"clock":[16,96,123],"power":[17,97,124],"and":[18,58,69,118],"decrease":[19],"the":[20,32,43,56,62,70,110,115,122,133],"total":[21],"area":[23,63,112],"in":[24,42,77,128],"synchronous":[26,116],"design.":[27],"To":[28],"acquire":[29],"these":[30],"advantages,":[31],"design":[33,117],"must":[34],"be":[35],"guaranteed":[36],"satisfy":[38],"certain":[39],"physical":[40],"constraints":[41],"process.":[45],"In":[46],"this":[47],"paper,":[48],"given":[49],"set":[51],"with":[55],"input":[57],"output":[59],"timing":[60],"constraints,":[61],"constraint":[64,72],"inside":[65],"any":[66,74],"partitioned":[67],"bin":[68,75],"capacity":[71],"on":[73,132],"edge":[76],"placement":[79],"plane,":[80],"an":[81],"efficient":[82],"routability-driven":[83],"approach":[84,106],"proposed":[86,105],"merge":[88],"for":[95,125],"reduction.":[98],"experimental":[100],"results":[101],"show":[102],"that":[103],"our":[104],"reduces":[107],"37.4%":[108],"maintain":[114],"saves":[119],"24.82%":[120],"five":[126],"examples":[127],"reasonable":[129],"CPU":[130],"time":[131],"average.":[134]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":4}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}