{"id":"https://openalex.org/W2014812420","doi":"https://doi.org/10.1109/iccd.2010.5647775","title":"Microarchitecture aware gate sizing: A framework for circuit-architecture co-optimization","display_name":"Microarchitecture aware gate sizing: A framework for circuit-architecture co-optimization","publication_year":2010,"publication_date":"2010-10-01","ids":{"openalex":"https://openalex.org/W2014812420","doi":"https://doi.org/10.1109/iccd.2010.5647775","mag":"2014812420"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.2010.5647775","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2010.5647775","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 IEEE International Conference on Computer Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5068885938","display_name":"Sanghamitra Roy","orcid":"https://orcid.org/0000-0002-3927-1612"},"institutions":[{"id":"https://openalex.org/I121980950","display_name":"Utah State University","ror":"https://ror.org/00h6set76","country_code":"US","type":"education","lineage":["https://openalex.org/I121980950"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Sanghamitra Roy","raw_affiliation_strings":["Electrical and Computer Engineering, Utah State University, USA"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering, Utah State University, USA","institution_ids":["https://openalex.org/I121980950"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101594477","display_name":"Koushik Chakraborty","orcid":"https://orcid.org/0000-0003-0228-2737"},"institutions":[{"id":"https://openalex.org/I121980950","display_name":"Utah State University","ror":"https://ror.org/00h6set76","country_code":"US","type":"education","lineage":["https://openalex.org/I121980950"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Koushik Chakraborty","raw_affiliation_strings":["Electrical and Computer Engineering, Utah State University, USA"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering, Utah State University, USA","institution_ids":["https://openalex.org/I121980950"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5068885938"],"corresponding_institution_ids":["https://openalex.org/I121980950"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.09309049,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"222","last_page":"228"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.8563964366912842},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.8013983964920044},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6628201007843018},{"id":"https://openalex.org/keywords/sizing","display_name":"Sizing","score":0.6589899063110352},{"id":"https://openalex.org/keywords/efficient-energy-use","display_name":"Efficient energy use","score":0.5627857446670532},{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.49799656867980957},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.49691441655158997},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4633503556251526},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.46095728874206543},{"id":"https://openalex.org/keywords/schematic","display_name":"Schematic","score":0.42637571692466736},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4101922810077667},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.36964479088783264},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21453627943992615},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1878703236579895}],"concepts":[{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.8563964366912842},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.8013983964920044},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6628201007843018},{"id":"https://openalex.org/C2777767291","wikidata":"https://www.wikidata.org/wiki/Q1080291","display_name":"Sizing","level":2,"score":0.6589899063110352},{"id":"https://openalex.org/C2742236","wikidata":"https://www.wikidata.org/wiki/Q924713","display_name":"Efficient energy use","level":2,"score":0.5627857446670532},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.49799656867980957},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.49691441655158997},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4633503556251526},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.46095728874206543},{"id":"https://openalex.org/C192328126","wikidata":"https://www.wikidata.org/wiki/Q4514647","display_name":"Schematic","level":2,"score":0.42637571692466736},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4101922810077667},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.36964479088783264},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21453627943992615},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1878703236579895},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccd.2010.5647775","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2010.5647775","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 IEEE International Conference on Computer Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8999999761581421}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":38,"referenced_works":["https://openalex.org/W1605013015","https://openalex.org/W1989716769","https://openalex.org/W2036853599","https://openalex.org/W2043340768","https://openalex.org/W2081379617","https://openalex.org/W2095942479","https://openalex.org/W2102727118","https://openalex.org/W2104205789","https://openalex.org/W2107493680","https://openalex.org/W2110388256","https://openalex.org/W2113227307","https://openalex.org/W2117299787","https://openalex.org/W2120635877","https://openalex.org/W2121082877","https://openalex.org/W2129763083","https://openalex.org/W2130494464","https://openalex.org/W2131172683","https://openalex.org/W2132178096","https://openalex.org/W2139344695","https://openalex.org/W2140984465","https://openalex.org/W2141907973","https://openalex.org/W2147793571","https://openalex.org/W2161537396","https://openalex.org/W2171115678","https://openalex.org/W3140903683","https://openalex.org/W3148862943","https://openalex.org/W4231119589","https://openalex.org/W4241323966","https://openalex.org/W4244405793","https://openalex.org/W4253029824","https://openalex.org/W4254850189","https://openalex.org/W4254851307","https://openalex.org/W6678286823","https://openalex.org/W6679541067","https://openalex.org/W6680663437","https://openalex.org/W6683816520","https://openalex.org/W6792941224","https://openalex.org/W6825925576"],"related_works":["https://openalex.org/W2109699519","https://openalex.org/W2006568360","https://openalex.org/W102726818","https://openalex.org/W4233616027","https://openalex.org/W2059591361","https://openalex.org/W970262775","https://openalex.org/W4244724753","https://openalex.org/W2535673728","https://openalex.org/W1972081536","https://openalex.org/W1831618318"],"abstract_inverted_index":{"Modern":[0],"high":[1],"performance":[2],"microprocessors":[3],"experience":[4],"substantially":[5],"lower":[6,19,52],"utilization":[7],"in":[8,84,99,120],"many":[9],"of":[10,77],"their":[11],"structural":[12],"components.":[13],"To":[14],"recover":[15],"energy":[16,42,123],"efficiency":[17,124],"from":[18],"utilization,":[20],"system":[21],"architects":[22],"resort":[23],"to":[24,67],"dynamic":[25,36],"voltage":[26,64],"frequency":[27],"scaling":[28],"(DVFS).":[29],"In":[30],"this":[31,69,95],"paper,":[32],"we":[33],"demonstrate":[34],"that":[35,46,80],"adaptations":[37],"using":[38],"DVFS":[39,130],"are":[40],"markedly":[41],"inefficient":[43],"than":[44],"techniques":[45],"design":[47],"circuits":[48],"ground":[49],"up":[50],"for":[51],"performance.":[53],"We":[54,93],"propose":[55],"a":[56,100],"novel":[57],"microarchitecture":[58],"aware":[59],"gate":[60,85,108],"sizing":[61,109],"and":[62,87,91],"threshold":[63],"assignment":[65],"algorithm":[66],"mitigate":[68],"current":[70],"limitation.":[71],"Our":[72,115],"technique":[73],"is":[74],"the":[75,121],"first":[76],"its":[78],"kind":[79],"exploits":[81],"architectural":[82,113],"slack":[83],"sizing,":[86],"leverages":[88],"on-chip":[89],"redundancy":[90],"slack.":[92],"evaluate":[94],"circuit-architectural":[96],"co-optimization":[97],"framework":[98],"superscalar":[101],"processor":[102],"by":[103],"combining":[104],"standard":[105],"cell":[106],"based":[107],"flows":[110],"with":[111],"state-of-the-art":[112],"simulation.":[114],"results":[116],"show":[117],"17-46%":[118],"improvement":[119],"datapath":[122],"over":[125],"traditional":[126],"circuit":[127],"designs":[128],"incorporating":[129],"schemes.":[131]},"counts_by_year":[{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}