{"id":"https://openalex.org/W2109015923","doi":"https://doi.org/10.1109/iccd.2009.5413171","title":"Impact analysis of performance faults in modern microprocessors","display_name":"Impact analysis of performance faults in modern microprocessors","publication_year":2009,"publication_date":"2009-10-01","ids":{"openalex":"https://openalex.org/W2109015923","doi":"https://doi.org/10.1109/iccd.2009.5413171","mag":"2109015923"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.2009.5413171","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2009.5413171","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International Conference on Computer Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5079088715","display_name":"Naghmeh Karimi","orcid":"https://orcid.org/0000-0002-5825-6637"},"institutions":[{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]}],"countries":["IR"],"is_corresponding":true,"raw_author_name":"Naghmeh Karimi","raw_affiliation_strings":["ECE Department, University of Tehran, Iran","ECE Department, University of Tehran,"],"affiliations":[{"raw_affiliation_string":"ECE Department, University of Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]},{"raw_affiliation_string":"ECE Department, University of Tehran,","institution_ids":["https://openalex.org/I23946033"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043325974","display_name":"Michail Maniatakos","orcid":"https://orcid.org/0000-0001-6899-0651"},"institutions":[{"id":"https://openalex.org/I32971472","display_name":"Yale University","ror":"https://ror.org/03v76x132","country_code":"US","type":"education","lineage":["https://openalex.org/I32971472"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Michail Maniatakos","raw_affiliation_strings":["EE Department, Yale University, USA","EE Department, Yale University"],"affiliations":[{"raw_affiliation_string":"EE Department, Yale University, USA","institution_ids":["https://openalex.org/I32971472"]},{"raw_affiliation_string":"EE Department, Yale University","institution_ids":["https://openalex.org/I32971472"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111987206","display_name":"Chandra Tirumurti","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chandra Tirumurti","raw_affiliation_strings":["Strategic CAD Laboratories, Intel Corporation, USA","Strategic CAD Lab, Intel Corporation#TAB#"],"affiliations":[{"raw_affiliation_string":"Strategic CAD Laboratories, Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Strategic CAD Lab, Intel Corporation#TAB#","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036507220","display_name":"Abhijit Jas","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Abhijit Jas","raw_affiliation_strings":["Validation and Test Solutions, Intel Corporation, USA","Validation and Test Solutions, Intel Corporation"],"affiliations":[{"raw_affiliation_string":"Validation and Test Solutions, Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Validation and Test Solutions, Intel Corporation","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5078818440","display_name":"Yiorgos Makris","orcid":"https://orcid.org/0000-0002-4322-0068"},"institutions":[{"id":"https://openalex.org/I32971472","display_name":"Yale University","ror":"https://ror.org/03v76x132","country_code":"US","type":"education","lineage":["https://openalex.org/I32971472"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yiorgos Makris","raw_affiliation_strings":["EE Department, Yale University, USA","EE Department, Yale University"],"affiliations":[{"raw_affiliation_string":"EE Department, Yale University, USA","institution_ids":["https://openalex.org/I32971472"]},{"raw_affiliation_string":"EE Department, Yale University","institution_ids":["https://openalex.org/I32971472"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5079088715"],"corresponding_institution_ids":["https://openalex.org/I23946033"],"apc_list":null,"apc_paid":null,"fwci":0.7915,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.73655649,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"91","last_page":"96"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.8723110556602478},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7620725035667419},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.7405219674110413},{"id":"https://openalex.org/keywords/variety","display_name":"Variety (cybernetics)","score":0.5387945771217346},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.49203726649284363},{"id":"https://openalex.org/keywords/branch-predictor","display_name":"Branch predictor","score":0.45869678258895874},{"id":"https://openalex.org/keywords/integer","display_name":"Integer (computer science)","score":0.4474949538707733},{"id":"https://openalex.org/keywords/fault","display_name":"Fault (geology)","score":0.4303600788116455},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.38635435700416565},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.35591503977775574},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.32199546694755554},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.16351181268692017},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1187448799610138},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.07344022393226624}],"concepts":[{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.8723110556602478},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7620725035667419},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.7405219674110413},{"id":"https://openalex.org/C136197465","wikidata":"https://www.wikidata.org/wiki/Q1729295","display_name":"Variety (cybernetics)","level":2,"score":0.5387945771217346},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.49203726649284363},{"id":"https://openalex.org/C168522837","wikidata":"https://www.wikidata.org/wiki/Q679552","display_name":"Branch predictor","level":2,"score":0.45869678258895874},{"id":"https://openalex.org/C97137487","wikidata":"https://www.wikidata.org/wiki/Q729138","display_name":"Integer (computer science)","level":2,"score":0.4474949538707733},{"id":"https://openalex.org/C175551986","wikidata":"https://www.wikidata.org/wiki/Q47089","display_name":"Fault (geology)","level":2,"score":0.4303600788116455},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.38635435700416565},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.35591503977775574},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.32199546694755554},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.16351181268692017},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1187448799610138},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.07344022393226624},{"id":"https://openalex.org/C127313418","wikidata":"https://www.wikidata.org/wiki/Q1069","display_name":"Geology","level":0,"score":0.0},{"id":"https://openalex.org/C165205528","wikidata":"https://www.wikidata.org/wiki/Q83371","display_name":"Seismology","level":1,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccd.2009.5413171","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2009.5413171","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International Conference on Computer Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":28,"referenced_works":["https://openalex.org/W1569032152","https://openalex.org/W1575200043","https://openalex.org/W1964769222","https://openalex.org/W1976431848","https://openalex.org/W2052887509","https://openalex.org/W2095617471","https://openalex.org/W2100110579","https://openalex.org/W2107822077","https://openalex.org/W2111228344","https://openalex.org/W2112438883","https://openalex.org/W2113627024","https://openalex.org/W2121494648","https://openalex.org/W2130363691","https://openalex.org/W2132214193","https://openalex.org/W2139338109","https://openalex.org/W2143285027","https://openalex.org/W2144764850","https://openalex.org/W2153243017","https://openalex.org/W2163820265","https://openalex.org/W2167069171","https://openalex.org/W4244652158","https://openalex.org/W4247080994","https://openalex.org/W4247641071","https://openalex.org/W6634019501","https://openalex.org/W6634313747","https://openalex.org/W6644399071","https://openalex.org/W6674622368","https://openalex.org/W6679664950"],"related_works":["https://openalex.org/W2061007994","https://openalex.org/W2408643487","https://openalex.org/W2145546531","https://openalex.org/W4256090683","https://openalex.org/W1586172811","https://openalex.org/W2389267844","https://openalex.org/W1667647204","https://openalex.org/W365166040","https://openalex.org/W2077619147","https://openalex.org/W2121217620"],"abstract_inverted_index":{"Towards":[0],"improving":[1],"performance,":[2],"modern":[3],"microprocessors":[4],"incorporate":[5],"a":[6,59],"variety":[7],"of":[8,25,55,89],"architectural":[9],"features,":[10],"such":[11,56],"as":[12],"branch":[13],"prediction":[14],"and":[15,79,96],"speculative":[16],"execution,":[17],"which":[18,66],"are":[19],"not":[20,35],"critical":[21],"to":[22],"the":[23,31,52,87],"correctness":[24],"their":[26],"operation.":[27],"While":[28],"faults":[29,57],"in":[30],"corresponding":[32],"hardware":[33,91],"may":[34,85],"necessarily":[36],"affect":[37],"functional":[38],"correctness,":[39],"they":[40],"may,":[41],"nevertheless,":[42],"adversely":[43],"impact":[44,54],"performance.":[45],"In":[46],"this":[47,83],"paper,":[48],"we":[49,67,80],"investigate":[50],"quantitatively":[51],"performance":[53,93],"using":[58],"superscalar,":[60],"dynamically-scheduled,":[61],"out-of-order,":[62],"Alpha-like":[63],"microprocessor,":[64],"on":[65],"execute":[68],"SPEC2000":[69],"integer":[70],"benchmarks.":[71],"We":[72],"provide":[73],"extensive":[74],"fault":[75],"simulation-based":[76],"experimental":[77],"results":[78],"discuss":[81],"how":[82],"information":[84],"guide":[86],"inclusion":[88],"additional":[90],"for":[92],"loss":[94],"recovery":[95],"yield":[97],"enhancement.":[98]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}