{"id":"https://openalex.org/W2159535130","doi":"https://doi.org/10.1109/iccd.2009.5413158","title":"Deterministic clock gating to eliminate wasteful activity due to wrong-path instructions in out-of-order superscalar processors","display_name":"Deterministic clock gating to eliminate wasteful activity due to wrong-path instructions in out-of-order superscalar processors","publication_year":2009,"publication_date":"2009-10-01","ids":{"openalex":"https://openalex.org/W2159535130","doi":"https://doi.org/10.1109/iccd.2009.5413158","mag":"2159535130"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.2009.5413158","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2009.5413158","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International Conference on Computer Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5015131186","display_name":"Nasir Mohyuddin","orcid":null},"institutions":[{"id":"https://openalex.org/I4210116219","display_name":"Engineering Systems (United States)","ror":"https://ror.org/02qg60849","country_code":"US","type":"company","lineage":["https://openalex.org/I4210116219"]},{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Nasir Mohyuddin","raw_affiliation_strings":["Department of Electrical Engineering (Systems), University of Southern California, Los Angeles, CA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering (Systems), University of Southern California, Los Angeles, CA, USA","institution_ids":["https://openalex.org/I1174212","https://openalex.org/I4210116219"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5029501970","display_name":"Kimish Patel","orcid":null},"institutions":[{"id":"https://openalex.org/I4210116219","display_name":"Engineering Systems (United States)","ror":"https://ror.org/02qg60849","country_code":"US","type":"company","lineage":["https://openalex.org/I4210116219"]},{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kimish Patel","raw_affiliation_strings":["Department of Electrical Engineering (Systems), University of Southern California, Los Angeles, CA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering (Systems), University of Southern California, Los Angeles, CA, USA","institution_ids":["https://openalex.org/I1174212","https://openalex.org/I4210116219"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5044650311","display_name":"Massoud Pedram","orcid":"https://orcid.org/0000-0002-2677-7307"},"institutions":[{"id":"https://openalex.org/I4210116219","display_name":"Engineering Systems (United States)","ror":"https://ror.org/02qg60849","country_code":"US","type":"company","lineage":["https://openalex.org/I4210116219"]},{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Massoud Pedram","raw_affiliation_strings":["Department of Electrical Engineering (Systems), University of Southern California, Los Angeles, CA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering (Systems), University of Southern California, Los Angeles, CA, USA","institution_ids":["https://openalex.org/I1174212","https://openalex.org/I4210116219"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5015131186"],"corresponding_institution_ids":["https://openalex.org/I1174212","https://openalex.org/I4210116219"],"apc_list":null,"apc_paid":null,"fwci":0.3048,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.66396608,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"166","last_page":"172"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.8259282112121582},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7603657841682434},{"id":"https://openalex.org/keywords/branch-predictor","display_name":"Branch predictor","score":0.6386900544166565},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.599665105342865},{"id":"https://openalex.org/keywords/idle","display_name":"Idle","score":0.5752072930335999},{"id":"https://openalex.org/keywords/gating","display_name":"Gating","score":0.5680273771286011},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.5296487808227539},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5111988186836243},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4474501609802246},{"id":"https://openalex.org/keywords/cpu-multiplier","display_name":"CPU multiplier","score":0.4411625266075134},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.4339252710342407},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.43378984928131104},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.4234987795352936},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3876464068889618},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.37028568983078003},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.17461499571800232},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.10264706611633301},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.09492072463035583}],"concepts":[{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.8259282112121582},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7603657841682434},{"id":"https://openalex.org/C168522837","wikidata":"https://www.wikidata.org/wiki/Q679552","display_name":"Branch predictor","level":2,"score":0.6386900544166565},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.599665105342865},{"id":"https://openalex.org/C16320812","wikidata":"https://www.wikidata.org/wiki/Q1812200","display_name":"Idle","level":2,"score":0.5752072930335999},{"id":"https://openalex.org/C194544171","wikidata":"https://www.wikidata.org/wiki/Q21105679","display_name":"Gating","level":2,"score":0.5680273771286011},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.5296487808227539},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5111988186836243},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4474501609802246},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.4411625266075134},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.4339252710342407},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.43378984928131104},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.4234987795352936},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3876464068889618},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.37028568983078003},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.17461499571800232},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.10264706611633301},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.09492072463035583},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C42407357","wikidata":"https://www.wikidata.org/wiki/Q521","display_name":"Physiology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/iccd.2009.5413158","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2009.5413158","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International Conference on Computer Design","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.398.2575","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.398.2575","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://iccd.et.tudelft.nl/2009/proceedings/166Mohyuddin.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.407.9538","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.407.9538","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://atrak.usc.edu/~massoud/Papers/deterministic-clockgating-iccd09.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8899999856948853,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W2013129990","https://openalex.org/W2095644119","https://openalex.org/W2102488630","https://openalex.org/W2102727118","https://openalex.org/W2108290909","https://openalex.org/W2113145722","https://openalex.org/W2117285153","https://openalex.org/W2118214977","https://openalex.org/W2120951490","https://openalex.org/W2161537396","https://openalex.org/W3140903683","https://openalex.org/W4256592301","https://openalex.org/W6677504465","https://openalex.org/W6792941224"],"related_works":["https://openalex.org/W2088914741","https://openalex.org/W4247180033","https://openalex.org/W2559451387","https://openalex.org/W2040807843","https://openalex.org/W3006003651","https://openalex.org/W4249038728","https://openalex.org/W2495024767","https://openalex.org/W1999924508","https://openalex.org/W2981406251","https://openalex.org/W2617666058"],"abstract_inverted_index":{"In":[0],"this":[1],"paper":[2],"we":[3],"present":[4],"deterministic":[5],"clock":[6,46,67,106],"gating":[7],"schemes":[8],"for":[9,61],"various":[10,48],"micro":[11],"architectural":[12],"blocks":[13],"of":[14,25,29,50,90,107,126,153],"a":[15],"modern":[16],"out-of-order":[17],"superscalar":[18],"processor.":[19],"We":[20],"propose":[21],"to":[22,45,99],"make":[23],"use":[24],"(1)":[26],"idle":[27,69],"stages":[28,49,70],"the":[30,66,88,100,105,113,154],"pipelined":[31],"function":[32],"units":[33],"(FUs)":[34],"and":[35,71,93,102,118,133],"(2)":[36],"wrong-path":[37,85,128],"instruction":[38,80],"execution":[39],"during":[40],"branch":[41,91],"mis-prediction,":[42],"in":[43,74,87,142],"order":[44],"gate":[47],"FUs.":[51],"The":[52,138],"baseline":[53,155],"Pipelined":[54],"Functional":[55],"unit":[56],"Clock":[57,81],"Gating":[58,82],"(PFCG),":[59],"presented":[60],"evaluation":[62],"purpose":[63],"only,":[64],"disables":[65,104],"on":[68,115],"thus":[72],"results":[73,141],"13.93%":[75],"chip-wide":[76,144],"energy":[77,145],"saving.":[78],"Wrong-path":[79],"(WPCG)":[83],"detects":[84],"instructions":[86,129],"event":[89],"mis-prediction":[92],"prevents":[94],"them":[95],"from":[96,135],"being":[97,136],"issued":[98],"FUs,":[101],"subsequently,":[103],"these":[108],"FUs":[109],"along":[110],"with":[111],"reducing":[112],"stress":[114],"register":[116],"file":[117],"cache.":[119],"Simulations":[120],"demonstrate":[121],"that":[122,152],"more":[123,150],"than":[124,151],"92%":[125],"all":[127],"can":[130],"be":[131],"detected":[132],"stopped":[134],"executed.":[137],"WPCG":[139],"architecture":[140],"16.26%":[143],"savings":[146],"which":[147],"is":[148],"2.33%":[149],"PFCG":[156],"scheme.":[157]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}