{"id":"https://openalex.org/W2141495440","doi":"https://doi.org/10.1109/iccd.2009.5413107","title":"A Technology-Agnostic Simulation Environment (TASE) for iterative custom IC design across processes","display_name":"A Technology-Agnostic Simulation Environment (TASE) for iterative custom IC design across processes","publication_year":2009,"publication_date":"2009-10-01","ids":{"openalex":"https://openalex.org/W2141495440","doi":"https://doi.org/10.1109/iccd.2009.5413107","mag":"2141495440"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.2009.5413107","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2009.5413107","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International Conference on Computer Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5050071437","display_name":"Satyanand Nalam","orcid":"https://orcid.org/0000-0002-6767-1752"},"institutions":[{"id":"https://openalex.org/I51556381","display_name":"University of Virginia","ror":"https://ror.org/0153tk833","country_code":"US","type":"education","lineage":["https://openalex.org/I51556381"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Satyanand Nalam","raw_affiliation_strings":["University of Virginia, USA","University of Virgnia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Virginia, USA","institution_ids":["https://openalex.org/I51556381"]},{"raw_affiliation_string":"University of Virgnia","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5089769405","display_name":"Mudit Bhargava","orcid":"https://orcid.org/0000-0003-4503-2260"},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mudit Bhargava","raw_affiliation_strings":["Carnegie Mellon University, USA","Carnegie Mellon University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Carnegie Mellon University, USA","institution_ids":["https://openalex.org/I74973139"]},{"raw_affiliation_string":"Carnegie Mellon University","institution_ids":["https://openalex.org/I74973139"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038577925","display_name":"Kyle Ringgenberg","orcid":null},"institutions":[{"id":"https://openalex.org/I51556381","display_name":"University of Virginia","ror":"https://ror.org/0153tk833","country_code":"US","type":"education","lineage":["https://openalex.org/I51556381"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kyle Ringgenberg","raw_affiliation_strings":["University of Virginia, USA","University of Virgnia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Virginia, USA","institution_ids":["https://openalex.org/I51556381"]},{"raw_affiliation_string":"University of Virgnia","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000377660","display_name":"Ken Mai","orcid":"https://orcid.org/0000-0002-9096-8757"},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ken Mai","raw_affiliation_strings":["Carnegie Mellon University, USA","Carnegie Mellon University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Carnegie Mellon University, USA","institution_ids":["https://openalex.org/I74973139"]},{"raw_affiliation_string":"Carnegie Mellon University","institution_ids":["https://openalex.org/I74973139"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5080557997","display_name":"Benton H. Calhoun","orcid":"https://orcid.org/0000-0002-3770-5050"},"institutions":[{"id":"https://openalex.org/I51556381","display_name":"University of Virginia","ror":"https://ror.org/0153tk833","country_code":"US","type":"education","lineage":["https://openalex.org/I51556381"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Benton H. Calhoun","raw_affiliation_strings":["University of Virginia, USA","University of Virgnia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Virginia, USA","institution_ids":["https://openalex.org/I51556381"]},{"raw_affiliation_string":"University of Virgnia","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5050071437"],"corresponding_institution_ids":["https://openalex.org/I51556381"],"apc_list":null,"apc_paid":null,"fwci":0.2681,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.60475019,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"523","last_page":"528"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/schematic","display_name":"Schematic","score":0.8940644264221191},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.765864372253418},{"id":"https://openalex.org/keywords/porting","display_name":"Porting","score":0.7474372386932373},{"id":"https://openalex.org/keywords/design-technology","display_name":"Design technology","score":0.5252851247787476},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.46305370330810547},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4412984251976013},{"id":"https://openalex.org/keywords/iterative-design","display_name":"Iterative design","score":0.41219183802604675},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.405932754278183},{"id":"https://openalex.org/keywords/systems-engineering","display_name":"Systems engineering","score":0.350211501121521},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.248482346534729},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.14740097522735596},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13624858856201172},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.10022646188735962}],"concepts":[{"id":"https://openalex.org/C192328126","wikidata":"https://www.wikidata.org/wiki/Q4514647","display_name":"Schematic","level":2,"score":0.8940644264221191},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.765864372253418},{"id":"https://openalex.org/C106251023","wikidata":"https://www.wikidata.org/wiki/Q851989","display_name":"Porting","level":3,"score":0.7474372386932373},{"id":"https://openalex.org/C179737136","wikidata":"https://www.wikidata.org/wiki/Q5264382","display_name":"Design technology","level":2,"score":0.5252851247787476},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.46305370330810547},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4412984251976013},{"id":"https://openalex.org/C106246047","wikidata":"https://www.wikidata.org/wiki/Q4928435","display_name":"Iterative design","level":3,"score":0.41219183802604675},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.405932754278183},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.350211501121521},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.248482346534729},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.14740097522735596},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13624858856201172},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.10022646188735962},{"id":"https://openalex.org/C2778648169","wikidata":"https://www.wikidata.org/wiki/Q967768","display_name":"Compatibility (geochemistry)","level":2,"score":0.0},{"id":"https://openalex.org/C42360764","wikidata":"https://www.wikidata.org/wiki/Q83588","display_name":"Chemical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccd.2009.5413107","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2009.5413107","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International Conference on Computer Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.4300000071525574}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1965206671","https://openalex.org/W2002612140","https://openalex.org/W2100905115","https://openalex.org/W2108880814","https://openalex.org/W2125347149","https://openalex.org/W2153643257","https://openalex.org/W2157522838","https://openalex.org/W4234744634","https://openalex.org/W6676056936"],"related_works":["https://openalex.org/W4253195573","https://openalex.org/W2020934033","https://openalex.org/W2009204280","https://openalex.org/W63276784","https://openalex.org/W3011978806","https://openalex.org/W2156446048","https://openalex.org/W2059530328","https://openalex.org/W2163890360","https://openalex.org/W2148225649","https://openalex.org/W2138990110"],"abstract_inverted_index":{"A":[0],"designer's":[1,81],"intent":[2],"and":[3,9,27,38,83,104,131,179],"knowledge":[4,31,52,82],"about":[5],"the":[6,19,41,57,80,87,96,124,128,135,143,148,159,172],"critical":[7],"issues":[8],"trade-offs":[10,130],"underlying":[11,129],"a":[12,49,64,72,91,108,111,184],"custom":[13,168],"circuit":[14],"design":[15,25,46,118,132],"are":[16,139,151],"implicit":[17],"in":[18,44,155,187],"simulations":[20,103],"she":[21],"sets":[22],"up":[23],"for":[24,183],"creation":[26],"verification.":[28],"However,":[29],"this":[30,51],"is":[32,53,71],"tightly":[33],"conjoined":[34],"with":[35],"technology-specific":[36,88],"features":[37],"decoupled":[39],"from":[40,86],"final":[42],"schematic":[43,119],"traditional":[45],"flows.":[47],"As":[48],"result,":[50],"easily":[54],"lost":[55],"when":[56],"technology":[58,65],"specifics":[59],"change.":[60],"This":[61,114],"paper":[62],"presents":[63],"agnostic":[66],"simulation":[67,76],"environment":[68],"(TASE),":[69],"which":[70,150],"tool":[73],"that":[74,126,161],"uses":[75],"templates":[77],"to":[78,98,110,120,123,147,153,191],"capture":[79],"separate":[84],"it":[85],"components":[89],"of":[90,101,166,174],"simulation.":[92],"TASE":[93,175],"also":[94],"allows":[95,115],"designer":[97,144],"form":[99],"groups":[100],"related":[102],"port":[105],"them":[106],"as":[107],"unit":[109],"new":[112,156],"technology.":[113],"an":[116],"actual":[117],"remain":[121],"tied":[122],"analyses":[125],"illuminate":[127],"issues,":[133],"unlike":[134],"case":[136],"where":[137],"schematics":[138],"ported":[140],"alone.":[141],"Giving":[142],"immediate":[145],"access":[146],"trade-offs,":[149],"likely":[152],"change":[154],"technologies,":[157],"accelerates":[158],"re-design":[160],"often":[162],"must":[163],"accompany":[164],"porting":[165],"complicated":[167],"circuits.":[169],"We":[170],"demonstrate":[171],"usefulness":[173],"by":[176],"investigating":[177],"Read":[178],"Write":[180],"noise":[181],"margins":[182],"6T":[185],"SRAM":[186],"predictive":[188],"technologies":[189],"down":[190],"16":[192],"nm.":[193]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2026-04-28T14:05:53.105641","created_date":"2025-10-10T00:00:00"}