{"id":"https://openalex.org/W2097922468","doi":"https://doi.org/10.1109/iccd.2008.4751922","title":"Issue system protection mechanisms","display_name":"Issue system protection mechanisms","publication_year":2008,"publication_date":"2008-10-01","ids":{"openalex":"https://openalex.org/W2097922468","doi":"https://doi.org/10.1109/iccd.2008.4751922","mag":"2097922468"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.2008.4751922","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2008.4751922","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International Conference on Computer Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111728780","display_name":"Pedro Chaparro","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Pedro Chaparro","raw_affiliation_strings":["Intel Barcelona Research Center, Intel Laboratories, Universitat Polilt\u00e8cnica de Catalunya, Barcelona, Spain","Intel Barcelona Res. Center, Intel Labs. - Univ. Politec. de Catalunya, Barcelona"],"affiliations":[{"raw_affiliation_string":"Intel Barcelona Research Center, Intel Laboratories, Universitat Polilt\u00e8cnica de Catalunya, Barcelona, Spain","institution_ids":[]},{"raw_affiliation_string":"Intel Barcelona Res. Center, Intel Labs. - Univ. Politec. de Catalunya, Barcelona","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020861175","display_name":"Jaume Abella","orcid":"https://orcid.org/0000-0001-7951-4028"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jaume Abella","raw_affiliation_strings":["Intel Barcelona Research Center, Intel Laboratories, Universitat Polilt\u00e8cnica de Catalunya, Barcelona, Spain","Intel Barcelona Res. Center, Intel Labs. - Univ. Politec. de Catalunya, Barcelona"],"affiliations":[{"raw_affiliation_string":"Intel Barcelona Research Center, Intel Laboratories, Universitat Polilt\u00e8cnica de Catalunya, Barcelona, Spain","institution_ids":[]},{"raw_affiliation_string":"Intel Barcelona Res. Center, Intel Labs. - Univ. Politec. de Catalunya, Barcelona","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103578976","display_name":"Javier Carretero","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Javier Carretero","raw_affiliation_strings":["Intel Barcelona Research Center, Intel Laboratories, Universitat Polilt\u00e8cnica de Catalunya, Barcelona, Spain","Intel Barcelona Res. Center, Intel Labs. - Univ. Politec. de Catalunya, Barcelona"],"affiliations":[{"raw_affiliation_string":"Intel Barcelona Research Center, Intel Laboratories, Universitat Polilt\u00e8cnica de Catalunya, Barcelona, Spain","institution_ids":[]},{"raw_affiliation_string":"Intel Barcelona Res. Center, Intel Labs. - Univ. Politec. de Catalunya, Barcelona","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5046613695","display_name":"Xavier Vera","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xavier Vera","raw_affiliation_strings":["Intel Barcelona Research Center, Intel Laboratories, Universitat Polilt\u00e8cnica de Catalunya, Barcelona, Spain","Intel Barcelona Res. Center, Intel Labs. - Univ. Politec. de Catalunya, Barcelona"],"affiliations":[{"raw_affiliation_string":"Intel Barcelona Research Center, Intel Laboratories, Universitat Polilt\u00e8cnica de Catalunya, Barcelona, Spain","institution_ids":[]},{"raw_affiliation_string":"Intel Barcelona Res. Center, Intel Labs. - Univ. Politec. de Catalunya, Barcelona","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5111728780"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":0.3329,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.64356948,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":"2","issue":null,"first_page":"599","last_page":"604"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.7170737981796265},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7127865552902222},{"id":"https://openalex.org/keywords/soft-error","display_name":"Soft error","score":0.565812349319458},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.5407547950744629},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.5081982612609863},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4366236925125122},{"id":"https://openalex.org/keywords/field","display_name":"Field (mathematics)","score":0.4348561763763428},{"id":"https://openalex.org/keywords/core","display_name":"Core (optical fiber)","score":0.4126734733581543},{"id":"https://openalex.org/keywords/transient","display_name":"Transient (computer programming)","score":0.41188132762908936},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.35283195972442627},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.18677911162376404},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.15351608395576477},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1503947675228119},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.13617059588432312},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10903719067573547}],"concepts":[{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.7170737981796265},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7127865552902222},{"id":"https://openalex.org/C154474529","wikidata":"https://www.wikidata.org/wiki/Q1658917","display_name":"Soft error","level":2,"score":0.565812349319458},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.5407547950744629},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.5081982612609863},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4366236925125122},{"id":"https://openalex.org/C9652623","wikidata":"https://www.wikidata.org/wiki/Q190109","display_name":"Field (mathematics)","level":2,"score":0.4348561763763428},{"id":"https://openalex.org/C2164484","wikidata":"https://www.wikidata.org/wiki/Q5170150","display_name":"Core (optical fiber)","level":2,"score":0.4126734733581543},{"id":"https://openalex.org/C2780799671","wikidata":"https://www.wikidata.org/wiki/Q17087362","display_name":"Transient (computer programming)","level":2,"score":0.41188132762908936},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.35283195972442627},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.18677911162376404},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.15351608395576477},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1503947675228119},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.13617059588432312},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10903719067573547},{"id":"https://openalex.org/C202444582","wikidata":"https://www.wikidata.org/wiki/Q837863","display_name":"Pure mathematics","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccd.2008.4751922","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2008.4751922","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International Conference on Computer Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W73121609","https://openalex.org/W1864485850","https://openalex.org/W1971851724","https://openalex.org/W1986236050","https://openalex.org/W2008482633","https://openalex.org/W2022740893","https://openalex.org/W2102480715","https://openalex.org/W2102863623","https://openalex.org/W2116015411","https://openalex.org/W2116059696","https://openalex.org/W2128941141","https://openalex.org/W2143068308","https://openalex.org/W2147435261","https://openalex.org/W2151845324","https://openalex.org/W2166987606","https://openalex.org/W2170653240","https://openalex.org/W2245151155","https://openalex.org/W2543171663","https://openalex.org/W4240029073","https://openalex.org/W4248445118","https://openalex.org/W4253094798","https://openalex.org/W4255602098","https://openalex.org/W6675837356"],"related_works":["https://openalex.org/W39373273","https://openalex.org/W2098026815","https://openalex.org/W2390545901","https://openalex.org/W2351709090","https://openalex.org/W975040225","https://openalex.org/W2735012529","https://openalex.org/W2732121450","https://openalex.org/W1619273082","https://openalex.org/W1604566864","https://openalex.org/W1970479385"],"abstract_inverted_index":{"Multi-core":[0],"microprocessors":[1],"require":[2],"reducing":[3],"the":[4,38,45,49,64,86,91,103,108,140],"FIT":[5,20,51],"(failures-in-time)":[6],"rate":[7],"per":[8],"core":[9],"drastically":[10],"to":[11,48,71,95,114,126,130],"enable":[12],"a":[13,19,67,131,155],"larger":[14],"number":[15,75,87],"of":[16,44,66,76,88,110,143],"cores":[17],"within":[18],"budget.":[21],"Since":[22],"large":[23],"arrays":[24],"like":[25],"caches":[26],"and":[27,128,135,146],"register":[28],"flies":[29],"are":[30,54,69],"typically":[31],"protected":[32],"with":[33],"either":[34],"ECC":[35],"or":[36],"parity,":[37],"issue":[39,141],"system":[40,142],"becomes":[41,99],"as":[42,97],"one":[43],"largest":[46],"contributors":[47],"core's":[50],"rate.":[52],"Soft-errors":[53],"an":[55,73],"important":[56],"concern":[57],"in":[58,79,90,139],"contemporary":[59],"microprocessors.":[60],"Particle":[61],"hits":[62],"on":[63],"components":[65],"processor":[68],"expected":[70,94],"create":[72],"increasing":[74],"transient":[77],"errors":[78,138],"each":[80],"new":[81],"microprocessor":[82],"generation.":[83],"In":[84],"addition,":[85],"hard-errors":[89],"field":[92],"is":[93],"grow":[96],"burn-in":[98],"less":[100],"effective.":[101],"Moreover,":[102],"continuous":[104],"device":[105],"shrinking":[106],"increases":[107],"likelihood":[109],"in-the-field":[111,137],"failures":[112],"due":[113],"rather":[115],"small":[116,156],"defects":[117],"exacerbated":[118],"by":[119],"degradation.":[120],"This":[121],"paper":[122],"proposes":[123],"on-line":[124],"mechanisms":[125,150],"detect":[127],"recover":[129],"consistent":[132],"state,":[133],"classify":[134],"confine":[136],"both":[144],"in-order":[145],"out-of-order":[147],"cores.":[148],"Such":[149],"provide":[151],"high":[152],"coverage":[153],"at":[154],"cost.":[157]},"counts_by_year":[{"year":2015,"cited_by_count":2},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}