{"id":"https://openalex.org/W2141154867","doi":"https://doi.org/10.1109/iccd.2008.4751900","title":"A macromodel technique for VLSI dynamic simulation by mapping pre-characterized transitions","display_name":"A macromodel technique for VLSI dynamic simulation by mapping pre-characterized transitions","publication_year":2008,"publication_date":"2008-10-01","ids":{"openalex":"https://openalex.org/W2141154867","doi":"https://doi.org/10.1109/iccd.2008.4751900","mag":"2141154867"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.2008.4751900","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2008.4751900","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International Conference on Computer Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5067223025","display_name":"Dimitrios Bountas","orcid":null},"institutions":[{"id":"https://openalex.org/I145722265","display_name":"University of Thessaly","ror":"https://ror.org/04v4g9h31","country_code":"GR","type":"education","lineage":["https://openalex.org/I145722265"]}],"countries":["GR"],"is_corresponding":true,"raw_author_name":"Dimitris Bountas","raw_affiliation_strings":["Department of Computer and Communication Engineering, University of Thessally, Volos, Greece","Dept. of Comput. & Commun. Eng. Volos, Univ. of Thessaly, Volos"],"affiliations":[{"raw_affiliation_string":"Department of Computer and Communication Engineering, University of Thessally, Volos, Greece","institution_ids":["https://openalex.org/I145722265"]},{"raw_affiliation_string":"Dept. of Comput. & Commun. Eng. Volos, Univ. of Thessaly, Volos","institution_ids":["https://openalex.org/I145722265"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065041833","display_name":"Georgios Stamoulis","orcid":"https://orcid.org/0000-0001-7248-8197"},"institutions":[{"id":"https://openalex.org/I145722265","display_name":"University of Thessaly","ror":"https://ror.org/04v4g9h31","country_code":"GR","type":"education","lineage":["https://openalex.org/I145722265"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Georgios Stamoulis","raw_affiliation_strings":["Department of Computer and Communication Engineering, University of Thessally, Volos, Greece","Dept. of Comput. & Commun. Eng. Volos, Univ. of Thessaly, Volos"],"affiliations":[{"raw_affiliation_string":"Department of Computer and Communication Engineering, University of Thessally, Volos, Greece","institution_ids":["https://openalex.org/I145722265"]},{"raw_affiliation_string":"Dept. of Comput. & Commun. Eng. Volos, Univ. of Thessaly, Volos","institution_ids":["https://openalex.org/I145722265"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112627040","display_name":"Nestoras Evmorfopoulos","orcid":null},"institutions":[{"id":"https://openalex.org/I145722265","display_name":"University of Thessaly","ror":"https://ror.org/04v4g9h31","country_code":"GR","type":"education","lineage":["https://openalex.org/I145722265"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Nestoras Evmorfopoulos","raw_affiliation_strings":["Department of Computer and Communication Engineering, University of Thessally, Volos, Greece","Dept. of Comput. & Commun. Eng. Volos, Univ. of Thessaly, Volos"],"affiliations":[{"raw_affiliation_string":"Department of Computer and Communication Engineering, University of Thessally, Volos, Greece","institution_ids":["https://openalex.org/I145722265"]},{"raw_affiliation_string":"Dept. of Comput. & Commun. Eng. Volos, Univ. of Thessaly, Volos","institution_ids":["https://openalex.org/I145722265"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5067223025"],"corresponding_institution_ids":["https://openalex.org/I145722265"],"apc_list":null,"apc_paid":null,"fwci":1.6647,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.85103802,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"450","last_page":"456"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/waveform","display_name":"Waveform","score":0.8079689741134644},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.7941336035728455},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.7403399348258972},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7224067449569702},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.6314291954040527},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.564775824546814},{"id":"https://openalex.org/keywords/dissipation","display_name":"Dissipation","score":0.5418885350227356},{"id":"https://openalex.org/keywords/transient","display_name":"Transient (computer programming)","score":0.5221538543701172},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.5006225109100342},{"id":"https://openalex.org/keywords/logic-simulation","display_name":"Logic simulation","score":0.4889298975467682},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4774896800518036},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.45317205786705017},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.44690531492233276},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4283674359321594},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4149889051914215},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.39109453558921814},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.3896896541118622},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3216245770454407},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.26193228363990784},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.18782272934913635},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14704084396362305},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.14190998673439026}],"concepts":[{"id":"https://openalex.org/C197424946","wikidata":"https://www.wikidata.org/wiki/Q1165717","display_name":"Waveform","level":3,"score":0.8079689741134644},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.7941336035728455},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.7403399348258972},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7224067449569702},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6314291954040527},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.564775824546814},{"id":"https://openalex.org/C135402231","wikidata":"https://www.wikidata.org/wiki/Q898440","display_name":"Dissipation","level":2,"score":0.5418885350227356},{"id":"https://openalex.org/C2780799671","wikidata":"https://www.wikidata.org/wiki/Q17087362","display_name":"Transient (computer programming)","level":2,"score":0.5221538543701172},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.5006225109100342},{"id":"https://openalex.org/C64859876","wikidata":"https://www.wikidata.org/wiki/Q173673","display_name":"Logic simulation","level":3,"score":0.4889298975467682},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4774896800518036},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.45317205786705017},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.44690531492233276},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4283674359321594},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4149889051914215},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.39109453558921814},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.3896896541118622},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3216245770454407},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.26193228363990784},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.18782272934913635},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14704084396362305},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.14190998673439026},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iccd.2008.4751900","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2008.4751900","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International Conference on Computer Design","raw_type":"proceedings-article"},{"id":"pmh:oai:ir.lib.uth.gr:11615/26420","is_oa":false,"landing_page_url":"http://hdl.handle.net/11615/26420","pdf_url":null,"source":{"id":"https://openalex.org/S4306400243","display_name":"University of Thessaly Institutional Repository (University of Thessaly)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I145722265","host_organization_name":"University of Thessaly","host_organization_lineage":["https://openalex.org/I145722265"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.scopus.com/inward/record.url?eid=2-s2.0-62349111937&partnerID=40&md5=c3b697ed2d1d1e22c698c4421778028c","raw_type":"conferenceItem"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.4000000059604645,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1817545098","https://openalex.org/W1988133210","https://openalex.org/W2009950823","https://openalex.org/W2023075074","https://openalex.org/W2065120607","https://openalex.org/W2130601386","https://openalex.org/W2144272826","https://openalex.org/W2163921999","https://openalex.org/W3148065654","https://openalex.org/W4230035938","https://openalex.org/W6647424666"],"related_works":["https://openalex.org/W3153609139","https://openalex.org/W2767573821","https://openalex.org/W2139611791","https://openalex.org/W3139874452","https://openalex.org/W2611789520","https://openalex.org/W2013538287","https://openalex.org/W2925003042","https://openalex.org/W2044903484","https://openalex.org/W2569609337","https://openalex.org/W4243758368"],"abstract_inverted_index":{"Accurate":[0],"simulation":[1,61],"of":[2,9,67,111],"digital":[3],"circuits":[4],"is":[5,39,47],"an":[6,30],"essential":[7],"part":[8],"the":[10,86,89,105],"design":[11,33],"process.":[12],"High":[13],"precision":[14,37],"models":[15],"are":[16],"generally":[17],"used":[18],"to":[19,119],"confirm":[20],"logic":[21],"behavior":[22],"and":[23,45,53,88],"estimate":[24],"power":[25],"dissipation,":[26],"which":[27],"has":[28],"become":[29],"extremely":[31],"important":[32],"parameter.":[34],"Unfortunately":[35],"high":[36],"analysis":[38],"expensive":[40],"in":[41,76,114],"computer":[42],"execution":[43],"time,":[44],"there":[46],"always":[48],"a":[49,58,65,77,112],"trade-off":[50],"between":[51],"accuracy":[52,101],"speed.":[54],"This":[55],"work":[56],"proposes":[57],"new":[59],"circuit":[60,113],"approach":[62],"by":[63,94],"storing":[64],"set":[66],"pre-characterized":[68],"transition":[69],"configurations":[70],"for":[71,103],"each":[72],"standard":[73],"library":[74],"cell":[75],"lookup":[78,81],"table.":[79],"The":[80,97],"table":[82],"contains":[83],"information":[84],"about":[85],"voltage":[87],"current":[90,109],"transient":[91],"waveform":[92,110],"produced":[93],"SPICE":[95,120],"simulation.":[96],"method":[98],"achieves":[99],"good":[100],"levels":[102],"yielding":[104],"total":[106],"or":[107,121],"partial":[108],"significantly":[115],"less":[116],"time":[117],"compared":[118],"other":[122],"commercial":[123],"tools.":[124]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}