{"id":"https://openalex.org/W2947416958","doi":"https://doi.org/10.1109/iccd.2008.4751853","title":"Design of application-specific 3D Networks-on-Chip architectures","display_name":"Design of application-specific 3D Networks-on-Chip architectures","publication_year":2008,"publication_date":"2008-10-01","ids":{"openalex":"https://openalex.org/W2947416958","doi":"https://doi.org/10.1109/iccd.2008.4751853","mag":"2947416958"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.2008.4751853","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2008.4751853","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International Conference on Computer Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5004878477","display_name":"Shan Yan","orcid":null},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shan Yan","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of California, San Diego, CA, USA","[Dept. of Electr. & Comput. Eng., Univ. of California, San Diego, CA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of California, San Diego, CA, USA","institution_ids":["https://openalex.org/I36258959"]},{"raw_affiliation_string":"[Dept. of Electr. & Comput. Eng., Univ. of California, San Diego, CA]","institution_ids":["https://openalex.org/I36258959"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5115588966","display_name":"Bill Lin","orcid":null},"institutions":[{"id":"https://openalex.org/I36258959","display_name":"University of California San Diego","ror":"https://ror.org/0168r3w48","country_code":"US","type":"education","lineage":["https://openalex.org/I36258959"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Bill Lin","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of California, San Diego, CA, USA","[Dept. of Electr. & Comput. Eng., Univ. of California, San Diego, CA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of California, San Diego, CA, USA","institution_ids":["https://openalex.org/I36258959"]},{"raw_affiliation_string":"[Dept. of Electr. & Comput. Eng., Univ. of California, San Diego, CA]","institution_ids":["https://openalex.org/I36258959"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I36258959"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.37603595,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"142","last_page":"149"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9955999851226807,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9922999739646912,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/router","display_name":"Router","score":0.8031817674636841},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.7177243828773499},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6459305882453918},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.6152167320251465},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.608102560043335},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.553791880607605},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.5431851148605347},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5335607528686523},{"id":"https://openalex.org/keywords/three-dimensional-integrated-circuit","display_name":"Three-dimensional integrated circuit","score":0.5307386517524719},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5232990384101868},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.500812292098999},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.49146711826324463},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.46817272901535034},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.3165662884712219},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.26397278904914856},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09623607993125916}],"concepts":[{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.8031817674636841},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.7177243828773499},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6459305882453918},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.6152167320251465},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.608102560043335},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.553791880607605},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.5431851148605347},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5335607528686523},{"id":"https://openalex.org/C59088047","wikidata":"https://www.wikidata.org/wiki/Q229370","display_name":"Three-dimensional integrated circuit","level":3,"score":0.5307386517524719},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5232990384101868},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.500812292098999},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.49146711826324463},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.46817272901535034},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.3165662884712219},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.26397278904914856},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09623607993125916},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":4,"locations":[{"id":"doi:10.1109/iccd.2008.4751853","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2008.4751853","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International Conference on Computer Design","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.184.390","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.184.390","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://cwc.ucsd.edu/%7Ebilllin/recent/iccd08_3dnoc.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.297.4387","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.297.4387","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://cwc.ucsd.edu/~billlin/recent/springer10_3D.pdf","raw_type":"text"},{"id":"mag:2947416958","is_oa":false,"landing_page_url":"https://dblp.uni-trier.de/db/series/icas/SPJ2011.html#YanL11","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":null,"raw_source_name":null,"raw_type":null}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.6100000143051147,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":30,"referenced_works":["https://openalex.org/W1541633348","https://openalex.org/W1974843053","https://openalex.org/W1998161811","https://openalex.org/W2023264348","https://openalex.org/W2054302810","https://openalex.org/W2079652913","https://openalex.org/W2103937255","https://openalex.org/W2106537813","https://openalex.org/W2106834190","https://openalex.org/W2117816012","https://openalex.org/W2118687888","https://openalex.org/W2132249049","https://openalex.org/W2132321891","https://openalex.org/W2141623997","https://openalex.org/W2157373341","https://openalex.org/W2160642395","https://openalex.org/W2161125053","https://openalex.org/W2172212694","https://openalex.org/W2538857334","https://openalex.org/W4239055271","https://openalex.org/W4241434521","https://openalex.org/W4253408813","https://openalex.org/W4253549065","https://openalex.org/W6651077136","https://openalex.org/W6660532380","https://openalex.org/W6675076578","https://openalex.org/W6675224354","https://openalex.org/W6677701396","https://openalex.org/W6682938842","https://openalex.org/W6683275698"],"related_works":["https://openalex.org/W2165667787","https://openalex.org/W2169169782","https://openalex.org/W1533703447","https://openalex.org/W1971041570","https://openalex.org/W2595347382","https://openalex.org/W2766373181","https://openalex.org/W2465806257","https://openalex.org/W2291552573","https://openalex.org/W2244913631","https://openalex.org/W1853065923","https://openalex.org/W205045693","https://openalex.org/W2106537813","https://openalex.org/W2754970123","https://openalex.org/W3186493969","https://openalex.org/W2188189903","https://openalex.org/W2117584697","https://openalex.org/W2099807878","https://openalex.org/W2539143739","https://openalex.org/W2051071423","https://openalex.org/W3198059568"],"abstract_inverted_index":{"The":[0],"increasing":[1],"viability":[2],"of":[3,21,45,66],"three":[4],"dimensional":[5],"(3D)":[6],"silicon":[7],"integration":[8],"technology":[9],"has":[10],"opened":[11],"new":[12],"opportunities":[13],"for":[14,53,72,100,108],"chip":[15,36],"design":[16,26,115],"innovations,":[17],"including":[18],"the":[19,43],"prospect":[20],"extending":[22],"emerging":[23],"systems-on-chip":[24],"(SoC)":[25],"paradigms":[27],"based":[28,93],"on":[29,94,113,123],"networks-on-chip":[30],"(NoC)":[31],"interconnection":[32],"architectures":[33,49],"to":[34],"3D":[35,73,141,160],"designs.":[37],"In":[38,78],"this":[39],"paper,":[40],"we":[41,80],"consider":[42],"problem":[44],"designing":[46],"application-specific":[47],"3D-NoC":[48,60,85,114],"that":[50,63,91,118],"are":[51],"optimized":[52,159],"a":[54,82,95,104,126,133,145,152],"given":[55],"application.":[56],"We":[57],"present":[58,81],"novel":[59],"synthesis":[61,86,120],"algorithms":[62],"make":[64],"use":[65],"accurate":[67],"power":[68,130,149],"and":[69,97,103,132,144,151],"delay":[70],"models":[71],"wiring":[74],"with":[75],"through-silicon":[76],"vias.":[77],"particular,":[79],"very":[83],"efficient":[84],"algorithm":[87],"called":[88],"ripup-reroute-and-router-merging":[89],"(RRRM),":[90],"is":[92],"rip-up":[96],"reroute":[98],"formulation":[99],"routing":[101],"flows":[102],"router":[105],"merging":[106],"procedure":[107],"network":[109],"optimization.":[110],"Experimental":[111],"results":[112,121],"cases":[116],"show":[117],"our":[119],"can":[122],"average":[124],"achieve":[125],"74%":[127],"reduction":[128,135,147,154],"in":[129,136,148,155],"consumption":[131,150],"17%":[134,153],"hop":[137,156],"count":[138,157],"over":[139,158],"regular":[140],"mesh":[142,161],"implementations":[143],"52%":[146],"implementations.":[162]},"counts_by_year":[{"year":2014,"cited_by_count":1}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}