{"id":"https://openalex.org/W2127406844","doi":"https://doi.org/10.1109/iccd.2008.4751851","title":"Gate planning during placement for gated clock network","display_name":"Gate planning during placement for gated clock network","publication_year":2008,"publication_date":"2008-10-01","ids":{"openalex":"https://openalex.org/W2127406844","doi":"https://doi.org/10.1109/iccd.2008.4751851","mag":"2127406844"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.2008.4751851","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2008.4751851","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International Conference on Computer Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5030467159","display_name":"Weixiang Shen","orcid":"https://orcid.org/0000-0002-4666-5126"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Weixiang Shen","raw_affiliation_strings":["EDA Laboratory, Departmentof Computer Science and Technology, Tsinghua University, Beijing, China","Dept-of Computer Science and Technology, Tsinghua University, Beijing,"],"affiliations":[{"raw_affiliation_string":"EDA Laboratory, Departmentof Computer Science and Technology, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]},{"raw_affiliation_string":"Dept-of Computer Science and Technology, Tsinghua University, Beijing,","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100894724","display_name":"Yici Cai","orcid":null},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yici Cai","raw_affiliation_strings":["EDA Laboratory, Departmentof Computer Science and Technology, Tsinghua University, Beijing, China","Dept-of Computer Science and Technology, Tsinghua University, Beijing,"],"affiliations":[{"raw_affiliation_string":"EDA Laboratory, Departmentof Computer Science and Technology, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]},{"raw_affiliation_string":"Dept-of Computer Science and Technology, Tsinghua University, Beijing,","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111768666","display_name":"Xianlong Hong","orcid":null},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xianlong Hong","raw_affiliation_strings":["EDA Laboratory, Departmentof Computer Science and Technology, Tsinghua University, Beijing, China","Dept-of Computer Science and Technology, Tsinghua University, Beijing,"],"affiliations":[{"raw_affiliation_string":"EDA Laboratory, Departmentof Computer Science and Technology, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]},{"raw_affiliation_string":"Dept-of Computer Science and Technology, Tsinghua University, Beijing,","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103246390","display_name":"Jiang Hu","orcid":"https://orcid.org/0000-0003-1157-7799"},"institutions":[{"id":"https://openalex.org/I91045830","display_name":"Texas A&M University","ror":"https://ror.org/01f5ytq51","country_code":"US","type":"education","lineage":["https://openalex.org/I91045830"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jiang Hu","raw_affiliation_strings":["Departmentof Electrical and Computer Engineering, Texas A and M University, College Station, TX, USA","Dept. of Electr. & Comput. Eng, Texas A&M Univ., College Station, TX#TAB#"],"affiliations":[{"raw_affiliation_string":"Departmentof Electrical and Computer Engineering, Texas A and M University, College Station, TX, USA","institution_ids":["https://openalex.org/I91045830"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng, Texas A&M Univ., College Station, TX#TAB#","institution_ids":["https://openalex.org/I91045830"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5030467159"],"corresponding_institution_ids":["https://openalex.org/I99065089"],"apc_list":null,"apc_paid":null,"fwci":0.9988,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.78665176,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"128","last_page":"133"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.9156004190444946},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.6688933372497559},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.6431292295455933},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6248467564582825},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.6166139245033264},{"id":"https://openalex.org/keywords/clock-network","display_name":"Clock network","score":0.6028351783752441},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.546059787273407},{"id":"https://openalex.org/keywords/cpu-multiplier","display_name":"CPU multiplier","score":0.519071638584137},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.47793108224868774},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.44771072268486023},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.4421137869358063},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4330863356590271},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4142165184020996},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.4116024971008301},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.3540903329849243},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.29828453063964844},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.22474294900894165},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.12564346194267273}],"concepts":[{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.9156004190444946},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.6688933372497559},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.6431292295455933},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6248467564582825},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.6166139245033264},{"id":"https://openalex.org/C2778182565","wikidata":"https://www.wikidata.org/wiki/Q1752879","display_name":"Clock network","level":5,"score":0.6028351783752441},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.546059787273407},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.519071638584137},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.47793108224868774},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.44771072268486023},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.4421137869358063},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4330863356590271},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4142165184020996},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.4116024971008301},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.3540903329849243},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.29828453063964844},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.22474294900894165},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.12564346194267273},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccd.2008.4751851","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2008.4751851","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International Conference on Computer Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Peace, Justice and strong institutions","score":0.5,"id":"https://metadata.un.org/sdg/16"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1819510856","https://openalex.org/W1970310355","https://openalex.org/W2023981464","https://openalex.org/W2095310213","https://openalex.org/W2096050740","https://openalex.org/W2128876681","https://openalex.org/W2129107674","https://openalex.org/W2136047350","https://openalex.org/W2136768070","https://openalex.org/W2142838686","https://openalex.org/W2143629014","https://openalex.org/W2150499679","https://openalex.org/W2163899785","https://openalex.org/W2172010755","https://openalex.org/W4249004757"],"related_works":["https://openalex.org/W2088914741","https://openalex.org/W4247180033","https://openalex.org/W2559451387","https://openalex.org/W2617666058","https://openalex.org/W2803012234","https://openalex.org/W2090213929","https://openalex.org/W2165139624","https://openalex.org/W3006003651","https://openalex.org/W2127892766","https://openalex.org/W2144282137"],"abstract_inverted_index":{"Clock":[0],"gating":[1,51],"is":[2,46,75,96,108,158,162],"a":[3,28,36,55,65,103,111,154,160,200],"popular":[4],"technique":[5,106],"for":[6],"reducing":[7],"power":[8,126,193,209,229],"dissipation":[9],"in":[10,71,90,139],"clock":[11,21,38,50,61,122,135,143,168,171,189],"network.":[12],"Although":[13],"there":[14],"have":[15,27],"been":[16],"numerous":[17],"research":[18],"efforts":[19],"on":[20,125,181,204,228],"gating,":[22],"the":[23,67,72,84,118,151,166,188,212,224],"previous":[24,179],"approaches":[25],"still":[26],"significant":[29],"weakness.":[30],"That":[31],"is,":[32],"they":[33],"usually":[34],"construct":[35],"gated":[37,60],"tree":[39,62,73,190],"after":[40],"cell":[41,44,80,113,116],"placement,":[42,117],"i.e.,":[43],"placement":[45,91,157,226],"performed":[47,163],"without":[48],"considering":[49],"and":[52,137,145,192,196,208,231],"may":[53],"generate":[54],"solution":[56],"unfriendly":[57],"to":[58,78,141,164,170],"subsequent":[59],"construction.":[63],"As":[64],"result,":[66],"control":[68],"gates":[69,123,136,169],"inserted":[70,133],"construction":[74],"very":[76,201],"likely":[77],"cause":[79],"overlap.":[81],"Even":[82],"though":[83],"overlap":[85],"can":[86],"be":[87],"eventually":[88],"removed":[89],"legalization,":[92],"remarkable":[93],"wirelength/power":[94],"overhead":[95],"incurred.":[97],"In":[98,128],"this":[99],"paper,":[100],"we":[101],"propose":[102],"gate":[104],"planning":[105,119],"which":[107],"integrated":[109],"with":[110,177,199,211],"partition-based":[112],"placer.":[114],"During":[115],"judiciously":[120],"inserts":[121],"based":[124],"estimation.":[127],"addition,":[129],"pseudo":[130],"edges":[131],"are":[132],"between":[134],"registers":[138],"order":[140],"reduce":[142],"wirelength":[144,191,207],"enable":[146],"long":[147],"shut-off":[148],"periods.":[149],"At":[150],"end,":[152],"when":[153],"relatively":[155],"detailed":[156],"obtained,":[159],"post-processing":[161],"degrade":[165],"inefficient":[167],"buffers.":[172],"We":[173],"compared":[174,210],"our":[175,221],"approach":[176],"recent":[178],"works":[180],"ISCAS89":[182],"benchmark":[183],"circuits.":[184],"Our":[185],"method":[186],"reduces":[187],"by":[194],"22.06%":[195],"40.80%,":[197],"respectively,":[198],"limited":[202],"increase":[203],"signal":[205],"nets":[206],"conventional":[213],"(register-oblivious)":[214],"placement.":[215],"The":[216],"results":[217],"also":[218],"indicate":[219],"that":[220],"algorithm":[222],"outperforms":[223],"clock-gating-oblivious":[225],"[9]":[227],"reduction":[230],"performance":[232],"improvement.":[233]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
