{"id":"https://openalex.org/W2137145694","doi":"https://doi.org/10.1109/iccd.2008.4751849","title":"Custom rotary clock router","display_name":"Custom rotary clock router","publication_year":2008,"publication_date":"2008-10-01","ids":{"openalex":"https://openalex.org/W2137145694","doi":"https://doi.org/10.1109/iccd.2008.4751849","mag":"2137145694"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.2008.4751849","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2008.4751849","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International Conference on Computer Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5072530511","display_name":"Vinayak Honkote","orcid":null},"institutions":[{"id":"https://openalex.org/I72816309","display_name":"Drexel University","ror":"https://ror.org/04bdffz58","country_code":"US","type":"education","lineage":["https://openalex.org/I72816309"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Vinayak Honkote","raw_affiliation_strings":["Electrical and Computer Engineering, Drexel University, Philadelphia, USA","Electr. & Comput. Eng., Drexel Univ., Philadelphia, PA"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering, Drexel University, Philadelphia, USA","institution_ids":["https://openalex.org/I72816309"]},{"raw_affiliation_string":"Electr. & Comput. Eng., Drexel Univ., Philadelphia, PA","institution_ids":["https://openalex.org/I72816309"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5081080799","display_name":"Bar\u0131\u015f Ta\u015fk\u0131n","orcid":"https://orcid.org/0000-0002-7631-5696"},"institutions":[{"id":"https://openalex.org/I72816309","display_name":"Drexel University","ror":"https://ror.org/04bdffz58","country_code":"US","type":"education","lineage":["https://openalex.org/I72816309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Baris Taskin","raw_affiliation_strings":["Electrical and Computer Engineering, Drexel University, Philadelphia, USA","Electr. & Comput. Eng., Drexel Univ., Philadelphia, PA"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering, Drexel University, Philadelphia, USA","institution_ids":["https://openalex.org/I72816309"]},{"raw_affiliation_string":"Electr. & Comput. Eng., Drexel Univ., Philadelphia, PA","institution_ids":["https://openalex.org/I72816309"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5072530511"],"corresponding_institution_ids":["https://openalex.org/I72816309"],"apc_list":null,"apc_paid":null,"fwci":2.3306,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.88812836,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"114","last_page":"119"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-network","display_name":"Clock network","score":0.6408601999282837},{"id":"https://openalex.org/keywords/router","display_name":"Router","score":0.5557399392127991},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.5405442118644714},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5357396602630615},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.5182654857635498},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.4933260977268219},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.4904188811779022},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.46030759811401367},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.4446823000907898},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.4214969575405121},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.3982684016227722},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3815820813179016},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3521648049354553},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3507249355316162},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.35010668635368347},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.17169415950775146}],"concepts":[{"id":"https://openalex.org/C2778182565","wikidata":"https://www.wikidata.org/wiki/Q1752879","display_name":"Clock network","level":5,"score":0.6408601999282837},{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.5557399392127991},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.5405442118644714},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5357396602630615},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.5182654857635498},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.4933260977268219},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.4904188811779022},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.46030759811401367},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.4446823000907898},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.4214969575405121},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.3982684016227722},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3815820813179016},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3521648049354553},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3507249355316162},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.35010668635368347},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.17169415950775146},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccd.2008.4751849","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2008.4751849","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International Conference on Computer Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7200000286102295,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1505272351","https://openalex.org/W1585683917","https://openalex.org/W1984845646","https://openalex.org/W2014857696","https://openalex.org/W2049078776","https://openalex.org/W2122724421","https://openalex.org/W2128060653","https://openalex.org/W2138857663","https://openalex.org/W2144402314","https://openalex.org/W2153580689","https://openalex.org/W2155670163","https://openalex.org/W2166694777","https://openalex.org/W4249481157","https://openalex.org/W4255697594","https://openalex.org/W6630124008","https://openalex.org/W6654074800"],"related_works":["https://openalex.org/W2088914741","https://openalex.org/W4247180033","https://openalex.org/W2559451387","https://openalex.org/W2144282137","https://openalex.org/W2127892766","https://openalex.org/W2617666058","https://openalex.org/W3006003651","https://openalex.org/W2384600254","https://openalex.org/W2090213929","https://openalex.org/W2165139624"],"abstract_inverted_index":{"Timing":[0],"closure":[1],"and":[2,75],"power":[3,38],"envelopes":[4],"for":[5,30,94,109,135],"contemporary":[6],"multi-core":[7],"chips":[8],"with":[9,126],"high":[10],"speed":[11],"clock":[12,16,33,56,71],"networks":[13,72],"make":[14],"the":[15,69,90,95,99,110,127],"distribution":[17],"design":[18,57],"a":[19,26,59,78],"challenging":[20],"task.":[21],"Resonant":[22],"rotary":[23,55,70,115],"clocking":[24,28,41],"is":[25,107,139],"novel":[27],"technology":[29],"multi-gigahertz":[31],"rate":[32],"generation":[34],"that":[35],"provides":[36],"minimal":[37],"dissipation.":[39],"Rotary":[40],"implementations":[42],"can":[43],"easily":[44],"provide":[45],"independent":[46],"synchronization":[47],"of":[48,63,112,133],"multiple":[49],"cores":[50],"as":[51,87],"well.":[52],"The":[53],"traditional":[54],"involves":[58],"regular":[60],"array":[61],"topology":[62,114],"oscillatory":[64,100],"rings.":[65,101,116],"In":[66,117],"this":[67],"paper,":[68],"are":[73,85],"designed":[74],"implemented":[76],"using":[77],"custom":[79,113],"ring":[80,83],"topology.":[81],"Custom":[82],"topologies":[84],"advantageous":[86],"they":[88],"reduce":[89],"total":[91],"tapping":[92,97,137],"wirelength":[93,138],"registers":[96],"onto":[98],"A":[102],"maze":[103],"router":[104],"based":[105],"algorithm":[106],"developed":[108],"implementation":[111],"experiments":[118],"performed":[119],"on":[120,141],"UCLA":[121],"IBM":[122],"R1-R5":[123],"benchmark":[124],"circuits":[125],"Elmore":[128],"delay":[129],"model,":[130],"an":[131],"improvement":[132],"11.04%":[134],"register":[136],"achieved":[140],"average.":[142]},"counts_by_year":[{"year":2016,"cited_by_count":2},{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}