{"id":"https://openalex.org/W2105127960","doi":"https://doi.org/10.1109/iccd.2008.4751837","title":"Configurable rectilinear Steiner tree construction for SoC and nano technologies","display_name":"Configurable rectilinear Steiner tree construction for SoC and nano technologies","publication_year":2008,"publication_date":"2008-10-01","ids":{"openalex":"https://openalex.org/W2105127960","doi":"https://doi.org/10.1109/iccd.2008.4751837","mag":"2105127960"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.2008.4751837","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2008.4751837","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International Conference on Computer Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5031004106","display_name":"Iris Hui-Ru Jiang","orcid":"https://orcid.org/0000-0002-4554-3442"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Iris Hui-Ru Jiang","raw_affiliation_strings":["Department of Electronics Engineering & Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan","Dept. of Electron. Eng. & Inst. of Electron., Nat. Chiao-Tung Univ., Hsinchu"],"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering & Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"Dept. of Electron. Eng. & Inst. of Electron., Nat. Chiao-Tung Univ., Hsinchu","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111627724","display_name":"Yen-Ting Yu","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yen-Ting Yu","raw_affiliation_strings":["Department of Electronics Engineering & Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan","Dept. of Electron. Eng. & Inst. of Electron., Nat. Chiao-Tung Univ., Hsinchu"],"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering & Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"Dept. of Electron. Eng. & Inst. of Electron., Nat. Chiao-Tung Univ., Hsinchu","institution_ids":["https://openalex.org/I148366613"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5031004106"],"corresponding_institution_ids":["https://openalex.org/I148366613"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.12766641,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"34","last_page":"39"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/steiner-tree-problem","display_name":"Steiner tree problem","score":0.9672198295593262},{"id":"https://openalex.org/keywords/obstacle","display_name":"Obstacle","score":0.8772231936454773},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.7614043951034546},{"id":"https://openalex.org/keywords/tree","display_name":"Tree (set theory)","score":0.6270992755889893},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.623075008392334},{"id":"https://openalex.org/keywords/layer","display_name":"Layer (electronics)","score":0.5244696140289307},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.4506932199001312},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.3373265266418457},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.33632850646972656},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.32823434472084045},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.22589805722236633},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.1787218451499939},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.13702961802482605},{"id":"https://openalex.org/keywords/combinatorics","display_name":"Combinatorics","score":0.11795338988304138},{"id":"https://openalex.org/keywords/nanotechnology","display_name":"Nanotechnology","score":0.09555184841156006},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.09466174244880676},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.07735732197761536}],"concepts":[{"id":"https://openalex.org/C76220878","wikidata":"https://www.wikidata.org/wiki/Q1764144","display_name":"Steiner tree problem","level":2,"score":0.9672198295593262},{"id":"https://openalex.org/C2776650193","wikidata":"https://www.wikidata.org/wiki/Q264661","display_name":"Obstacle","level":2,"score":0.8772231936454773},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.7614043951034546},{"id":"https://openalex.org/C113174947","wikidata":"https://www.wikidata.org/wiki/Q2859736","display_name":"Tree (set theory)","level":2,"score":0.6270992755889893},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.623075008392334},{"id":"https://openalex.org/C2779227376","wikidata":"https://www.wikidata.org/wiki/Q6505497","display_name":"Layer (electronics)","level":2,"score":0.5244696140289307},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.4506932199001312},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.3373265266418457},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.33632850646972656},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.32823434472084045},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.22589805722236633},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.1787218451499939},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.13702961802482605},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.11795338988304138},{"id":"https://openalex.org/C171250308","wikidata":"https://www.wikidata.org/wiki/Q11468","display_name":"Nanotechnology","level":1,"score":0.09555184841156006},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.09466174244880676},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.07735732197761536},{"id":"https://openalex.org/C199539241","wikidata":"https://www.wikidata.org/wiki/Q7748","display_name":"Law","level":1,"score":0.0},{"id":"https://openalex.org/C17744445","wikidata":"https://www.wikidata.org/wiki/Q36442","display_name":"Political science","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccd.2008.4751837","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2008.4751837","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International Conference on Computer Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Sustainable cities and communities","id":"https://metadata.un.org/sdg/11","score":0.41999998688697815}],"awards":[],"funders":[{"id":"https://openalex.org/F4320323900","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W73629738","https://openalex.org/W1508968487","https://openalex.org/W1538422958","https://openalex.org/W1977187766","https://openalex.org/W2011024254","https://openalex.org/W2020112047","https://openalex.org/W2028847061","https://openalex.org/W2054452185","https://openalex.org/W2117449332","https://openalex.org/W2123315514","https://openalex.org/W2123524254","https://openalex.org/W2132627508","https://openalex.org/W2752885492","https://openalex.org/W4251391716","https://openalex.org/W6678839516"],"related_works":["https://openalex.org/W2054452185","https://openalex.org/W2362006006","https://openalex.org/W2021808862","https://openalex.org/W2105127960","https://openalex.org/W2028847061","https://openalex.org/W2945692190","https://openalex.org/W2132668926","https://openalex.org/W3015807029","https://openalex.org/W2609144717","https://openalex.org/W4251514701"],"abstract_inverted_index":{"The":[0],"rectilinear":[1,50],"Steiner":[2,51],"minimal":[3],"tree":[4,52],"(RSMT)":[5],"problem":[6],"is":[7,60],"essential":[8],"in":[9],"physical":[10],"design.":[11],"Moreover,":[12],"the":[13,64],"variant":[14],"constraints":[15],"for":[16,34,46],"fabrication":[17],"issues,":[18],"including":[19],"obstacle":[20],"avoidance,":[21],"multiple":[22],"routing":[23,26],"layers,":[24],"layer-specific":[25],"directions,":[27],"cannot":[28],"be":[29],"ignored":[30],"during":[31],"RSMT":[32],"construction":[33],"modern":[35],"SoC":[36],"and":[37,62],"nano":[38],"technologies.":[39],"This":[40],"paper":[41],"proposes":[42],"a":[43],"construction-by-correction":[44],"approach":[45],"obstacle-avoiding":[47],"preferred":[48],"direction":[49],"construction.":[53],"Experimental":[54],"results":[55],"show":[56],"that":[57],"our":[58],"algorithm":[59],"promising":[61],"outperforms":[63],"state-of-the-art":[65],"works.":[66]},"counts_by_year":[{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}