{"id":"https://openalex.org/W2062173292","doi":"https://doi.org/10.1109/iccd.2007.4601881","title":"A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS","display_name":"A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS","publication_year":2007,"publication_date":"2007-10-01","ids":{"openalex":"https://openalex.org/W2062173292","doi":"https://doi.org/10.1109/iccd.2007.4601881","mag":"2062173292"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.2007.4601881","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2007.4601881","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 25th International Conference on Computer Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5098326904","display_name":"Amit Kumary","orcid":null},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Amit Kumary","raw_affiliation_strings":["Princeton University, Princeton, NJ, US"],"affiliations":[{"raw_affiliation_string":"Princeton University, Princeton, NJ, US","institution_ids":["https://openalex.org/I20089843"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5098370363","display_name":"Partha Kunduz","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Partha Kunduz","raw_affiliation_strings":["Microprocessor Technology Labs, Intel Corp., Santa Clara, CA 95052, USA"],"affiliations":[{"raw_affiliation_string":"Microprocessor Technology Labs, Intel Corp., Santa Clara, CA 95052, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100634933","display_name":"A. Singh","orcid":"https://orcid.org/0000-0003-3186-3098"},"institutions":[{"id":"https://openalex.org/I4210146682","display_name":"Intel (India)","ror":"https://ror.org/04f2n1245","country_code":"IN","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210146682"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Arvind P. Singhx","raw_affiliation_strings":["Intel Technology India Pvt Ltd., Airport Road, Bangalore, India 560017"],"affiliations":[{"raw_affiliation_string":"Intel Technology India Pvt Ltd., Airport Road, Bangalore, India 560017","institution_ids":["https://openalex.org/I4210146682"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5086114732","display_name":"Li-Shiuan Pehy","orcid":null},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Li-Shiuan Pehy","raw_affiliation_strings":["Dept. of Electrical Engineering, Princeton University, NJ 08544, USA"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical Engineering, Princeton University, NJ 08544, USA","institution_ids":["https://openalex.org/I20089843"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5098326905","display_name":"Niraj K. Jhay","orcid":null},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Niraj K. Jhay","raw_affiliation_strings":["Dept. of Electrical Engineering, Princeton University, NJ 08544, USA"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical Engineering, Princeton University, NJ 08544, USA","institution_ids":["https://openalex.org/I20089843"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5098326904"],"corresponding_institution_ids":["https://openalex.org/I20089843"],"apc_list":null,"apc_paid":null,"fwci":21.8917,"has_fulltext":false,"cited_by_count":271,"citation_normalized_percentile":{"value":0.99542377,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":100},"biblio":{"volume":null,"issue":null,"first_page":"63","last_page":"70"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10018","display_name":"Advancements in Battery Materials","score":0.991599977016449,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9879999756813049,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7038910388946533},{"id":"https://openalex.org/keywords/router","display_name":"Router","score":0.6932902336120605},{"id":"https://openalex.org/keywords/allocator","display_name":"Allocator","score":0.6328402757644653},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6024181842803955},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.472474068403244},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.3867032825946808},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.35175958275794983},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.18383905291557312}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7038910388946533},{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.6932902336120605},{"id":"https://openalex.org/C162262903","wikidata":"https://www.wikidata.org/wiki/Q343527","display_name":"Allocator","level":2,"score":0.6328402757644653},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6024181842803955},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.472474068403244},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.3867032825946808},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.35175958275794983},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.18383905291557312}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccd.2007.4601881","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2007.4601881","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 25th International Conference on Computer Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.5699999928474426}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1481733864","https://openalex.org/W1501077214","https://openalex.org/W1550639219","https://openalex.org/W2004076644","https://openalex.org/W2096383657","https://openalex.org/W2097560795","https://openalex.org/W2098246773","https://openalex.org/W2123184444","https://openalex.org/W2125357468","https://openalex.org/W2126169247","https://openalex.org/W2140122127","https://openalex.org/W2145336644","https://openalex.org/W2147471190","https://openalex.org/W2152788432","https://openalex.org/W2153733042","https://openalex.org/W2156475585","https://openalex.org/W2160642395","https://openalex.org/W2162332665","https://openalex.org/W2166925534","https://openalex.org/W4229732121","https://openalex.org/W6678665702","https://openalex.org/W6682461300"],"related_works":["https://openalex.org/W2113763229","https://openalex.org/W2052816277","https://openalex.org/W2167988973","https://openalex.org/W2603824091","https://openalex.org/W2560886726","https://openalex.org/W2091258882","https://openalex.org/W2541438272","https://openalex.org/W2013729863","https://openalex.org/W3006485811","https://openalex.org/W2510977931"],"abstract_inverted_index":{"As":[0],"chip":[1],"multiprocessors":[2],"(CMPs)":[3],"become":[4],"the":[5,14,22],"only":[6],"viable":[7],"way":[8],"to":[9,40,94,124,143],"scale":[10],"up":[11,151],"and":[12,37,44,52,98,101,109,134,157],"utilize":[13],"abundant":[15],"transistors":[16],"made":[17],"available":[18],"in":[19,75,181],"current":[20],"microprocessors,":[21],"design":[23,35,62,79,90,102,139],"of":[24,63,85,183],"on-chip":[25,65],"networks":[26,32],"is":[27],"becoming":[28],"critically":[29],"important.":[30],"These":[31],"face":[33],"unique":[34,96],"constraints":[36],"are":[38],"required":[39],"provide":[41],"extremely":[42],"fast":[43],"high":[45,107],"bandwidth":[46],"communication,":[47],"yet":[48],"meet":[49],"tight":[50],"power":[51,161],"area":[53,156],"budgets.":[54],"In":[55],"this":[56],"paper,":[57],"we":[58],"present":[59],"a":[60,70,105,115,129,135,166,176],"detailed":[61],"our":[64],"network":[66],"router":[67,118,149,186],"targeted":[68],"at":[69,162,170],"36-core":[71],"shared-memory":[72],"CMP":[73],"system":[74],"65nm":[76],"technology.":[77],"Our":[78,148],"targets":[80],"an":[81],"aggressive":[82],"clock":[83,172],"frequency":[84,173],"3.6GHz,":[86],"thus":[87],"posing":[88],"tough":[89],"challenges":[91],"that":[92],"led":[93],"several":[95],"circuit":[97],"microarchitectural":[99],"innovations":[100],"choices,":[103],"including":[104],"novel":[106],"throughput":[108],"low":[110],"latency":[111,169],"switch":[112],"allocation":[113],"mechanism,":[114],"non-speculative":[116],"single-cycle":[117,167],"pipeline":[119],"which":[120,140],"uses":[121,141],"advanced":[122],"bundles":[123],"remove":[125],"control":[126],"setup":[127],"overhead,":[128],"low-complexity":[130],"virtual":[131],"channel":[132],"allocator":[133],"dynamically-managed":[136],"shared":[137],"buffer":[138],"prefetching":[142],"minimize":[144],"critical":[145],"path":[146],"delay.":[147],"takes":[150],"1.19mm":[152],"<sup":[153],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[154],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[155],"expends":[158],"551":[159],"mW":[160],"10%":[163],"activity,":[164],"delivering":[165],"no-load":[168],"3.6GHz":[171],"while":[174],"achieving":[175],"peak":[177],"switching":[178],"data":[179],"rate":[180],"excess":[182],"4.6Tbits/s":[184],"per":[185],"node.":[187]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":7},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":6},{"year":2017,"cited_by_count":20},{"year":2016,"cited_by_count":16},{"year":2015,"cited_by_count":18},{"year":2014,"cited_by_count":28},{"year":2013,"cited_by_count":33},{"year":2012,"cited_by_count":29}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}