{"id":"https://openalex.org/W2169291699","doi":"https://doi.org/10.1109/iccd.2006.4380858","title":"Design and Implementation of the TRIPS Primary Memory System","display_name":"Design and Implementation of the TRIPS Primary Memory System","publication_year":2006,"publication_date":"2006-10-01","ids":{"openalex":"https://openalex.org/W2169291699","doi":"https://doi.org/10.1109/iccd.2006.4380858","mag":"2169291699"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.2006.4380858","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2006.4380858","pdf_url":null,"source":{"id":"https://openalex.org/S4210174938","display_name":"Proceedings, IEEE International Conference on Computer Design/Proceedings - IEEE International Conference on Computer Design","issn_l":"1063-6404","issn":["1063-6404","2576-6996"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 International Conference on Computer Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5030436580","display_name":"Simha Sethumadhavan","orcid":"https://orcid.org/0000-0002-6180-7153"},"institutions":[{"id":"https://openalex.org/I4210126846","display_name":"Information Technology Laboratory","ror":"https://ror.org/0440c3437","country_code":"US","type":"government","lineage":["https://openalex.org/I1321296531","https://openalex.org/I1343035065","https://openalex.org/I4210126846"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Simha Sethumadhavan","raw_affiliation_strings":["Computer Architecture and Technology Laboratory, Department of Computer Sciences, University of Technology, Austin, USA"],"affiliations":[{"raw_affiliation_string":"Computer Architecture and Technology Laboratory, Department of Computer Sciences, University of Technology, Austin, USA","institution_ids":["https://openalex.org/I4210126846"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045450841","display_name":"Robert McDonald","orcid":null},"institutions":[{"id":"https://openalex.org/I4210126846","display_name":"Information Technology Laboratory","ror":"https://ror.org/0440c3437","country_code":"US","type":"government","lineage":["https://openalex.org/I1321296531","https://openalex.org/I1343035065","https://openalex.org/I4210126846"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Robert McDonald","raw_affiliation_strings":["Computer Architecture and Technology Laboratory, Department of Computer Sciences, University of Technology, Austin, USA"],"affiliations":[{"raw_affiliation_string":"Computer Architecture and Technology Laboratory, Department of Computer Sciences, University of Technology, Austin, USA","institution_ids":["https://openalex.org/I4210126846"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076334479","display_name":"Rajagopalan Desikan","orcid":null},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rajagopalan Desikan","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Technology, Austin, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Technology, Austin, USA","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067337700","display_name":"Doug Burger","orcid":"https://orcid.org/0009-0006-6588-6596"},"institutions":[{"id":"https://openalex.org/I4210126846","display_name":"Information Technology Laboratory","ror":"https://ror.org/0440c3437","country_code":"US","type":"government","lineage":["https://openalex.org/I1321296531","https://openalex.org/I1343035065","https://openalex.org/I4210126846"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Doug Burger","raw_affiliation_strings":["Computer Architecture and Technology Laboratory, Department of Computer Sciences, University of Technology, Austin, USA"],"affiliations":[{"raw_affiliation_string":"Computer Architecture and Technology Laboratory, Department of Computer Sciences, University of Technology, Austin, USA","institution_ids":["https://openalex.org/I4210126846"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5063354509","display_name":"Stephen W. Keckler","orcid":"https://orcid.org/0000-0001-6701-6099"},"institutions":[{"id":"https://openalex.org/I4210126846","display_name":"Information Technology Laboratory","ror":"https://ror.org/0440c3437","country_code":"US","type":"government","lineage":["https://openalex.org/I1321296531","https://openalex.org/I1343035065","https://openalex.org/I4210126846"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Stephen W. Keckler","raw_affiliation_strings":["Computer Architecture and Technology Laboratory, Department of Computer Sciences, University of Technology, Austin, USA"],"affiliations":[{"raw_affiliation_string":"Computer Architecture and Technology Laboratory, Department of Computer Sciences, University of Technology, Austin, USA","institution_ids":["https://openalex.org/I4210126846"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5030436580"],"corresponding_institution_ids":["https://openalex.org/I4210126846"],"apc_list":null,"apc_paid":null,"fwci":2.96,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.91025641,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":"3","issue":null,"first_page":"470","last_page":"476"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8101749420166016},{"id":"https://openalex.org/keywords/non-uniform-memory-access","display_name":"Non-uniform memory access","score":0.6082084774971008},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.5580901503562927},{"id":"https://openalex.org/keywords/ibm","display_name":"IBM","score":0.541340172290802},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.5361526012420654},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.5268591642379761},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.5210046768188477},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.4982576370239258},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.45274078845977783},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4511687755584717},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4506412744522095},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4457724392414093},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.43459534645080566},{"id":"https://openalex.org/keywords/processor-design","display_name":"Processor design","score":0.4155840575695038},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.4115092158317566},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.3608180284500122},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.22974291443824768},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.22388657927513123},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.153238445520401}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8101749420166016},{"id":"https://openalex.org/C133371097","wikidata":"https://www.wikidata.org/wiki/Q868014","display_name":"Non-uniform memory access","level":5,"score":0.6082084774971008},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.5580901503562927},{"id":"https://openalex.org/C70388272","wikidata":"https://www.wikidata.org/wiki/Q5968558","display_name":"IBM","level":2,"score":0.541340172290802},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.5361526012420654},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.5268591642379761},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.5210046768188477},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.4982576370239258},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.45274078845977783},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4511687755584717},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4506412744522095},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4457724392414093},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.43459534645080566},{"id":"https://openalex.org/C526435321","wikidata":"https://www.wikidata.org/wiki/Q1303814","display_name":"Processor design","level":2,"score":0.4155840575695038},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.4115092158317566},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.3608180284500122},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.22974291443824768},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.22388657927513123},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.153238445520401},{"id":"https://openalex.org/C171250308","wikidata":"https://www.wikidata.org/wiki/Q11468","display_name":"Nanotechnology","level":1,"score":0.0},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/iccd.2006.4380858","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2006.4380858","pdf_url":null,"source":{"id":"https://openalex.org/S4210174938","display_name":"Proceedings, IEEE International Conference on Computer Design/Proceedings - IEEE International Conference on Computer Design","issn_l":"1063-6404","issn":["1063-6404","2576-6996"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 International Conference on Computer Design","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.259.4672","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.259.4672","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cecs.uci.edu/%7Epapers/iccd2006/papers/paper_145.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.80.915","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.80.915","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cs.utexas.edu/users/simha/publications/dtile.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320332180","display_name":"Defense Advanced Research Projects Agency","ror":"https://ror.org/02caytj08"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W2064909421","https://openalex.org/W2083868341","https://openalex.org/W2101735776","https://openalex.org/W2147345262","https://openalex.org/W2163820265","https://openalex.org/W4236272793","https://openalex.org/W4244227015","https://openalex.org/W6683865707"],"related_works":["https://openalex.org/W1598433531","https://openalex.org/W1974211070","https://openalex.org/W126098351","https://openalex.org/W4229967581","https://openalex.org/W2021929420","https://openalex.org/W2247651031","https://openalex.org/W1975698617","https://openalex.org/W4295235956","https://openalex.org/W2123955550","https://openalex.org/W79990711"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3],"describe":[4,94],"the":[5,10,15,20,31,90,97,100,108,117,121,126,134,137],"design":[6,77,104,127,130],"and":[7,24,54,60,64,86,111,116],"implementation":[8],"of":[9,14,28,51,89,99,105,107,125,136],"primary":[11,32],"memory":[12,29,33,47,101,139],"system":[13,34,140],"TRIPS":[16],"processor.":[17],"To":[18],"match":[19],"aggressive":[21,49,145],"execution":[22],"bandwidth":[23],"support":[25,42],"high":[26],"levels":[27],"parallelism,":[30],"is":[35,141],"completely":[36],"partitioned":[37,138],"into":[38],"four":[39,58],"banks,":[40],"can":[41],"up":[43,56,65],"to":[44,57,66,71,143],"256":[45],"in-flight":[46,52],"instructions,":[48],"reordering":[50],"loads":[53,59],"stores,":[55],"stores":[61],"every":[62],"cycle":[63],"64":[67],"outstanding":[68],"cache":[69,74],"misses":[70],"sixteen":[72],"different":[73],"lines.":[75],"The":[76],"was":[78],"implemented":[79],"using":[80],"IBM":[81],"130":[82],"nm":[83],"ASIC":[84],"technology":[85],"occupies":[87],"21%":[88],"processor":[91],"area.":[92],"We":[93],"in":[95],"detail":[96],"microarchitecture":[98],"system,":[102],"detailed":[103],"two":[106],"most":[109],"complex":[110],"interesting":[112],"components":[113],"-the":[114],"LSQ":[115],"MHU":[118],"-and":[119],"discuss":[120],"rationale":[122],"behind":[123],"some":[124],"decisions.":[128],"Our":[129],"experience":[131],"suggests":[132],"that":[133],"complexity":[135],"comparable":[142],"less":[144],"centralized":[146],"implementations.":[147]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":4}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
