{"id":"https://openalex.org/W2103657038","doi":"https://doi.org/10.1109/iccd.2006.4380841","title":"Generic Architecture Description for Retargetable Compilation and Synthesis of Application-Specific Pipelined IPs","display_name":"Generic Architecture Description for Retargetable Compilation and Synthesis of Application-Specific Pipelined IPs","publication_year":2006,"publication_date":"2006-10-01","ids":{"openalex":"https://openalex.org/W2103657038","doi":"https://doi.org/10.1109/iccd.2006.4380841","mag":"2103657038"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.2006.4380841","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2006.4380841","pdf_url":null,"source":{"id":"https://openalex.org/S4210174938","display_name":"Proceedings, IEEE International Conference on Computer Design/Proceedings - IEEE International Conference on Computer Design","issn_l":"1063-6404","issn":["1063-6404","2576-6996"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 International Conference on Computer Design","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5072017278","display_name":"Bita Gorjiara","orcid":null},"institutions":[{"id":"https://openalex.org/I204250578","display_name":"University of California, Irvine","ror":"https://ror.org/04gyf1771","country_code":"US","type":"education","lineage":["https://openalex.org/I204250578"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Bita Gorjiara","raw_affiliation_strings":["Center for Embedded Computer Systems, University of California, Irvine, USA","Center for Embedded Computer Systems, University of California, Irvine. bgorjiar@cecs.uci.edu"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Center for Embedded Computer Systems, University of California, Irvine, USA","institution_ids":["https://openalex.org/I204250578"]},{"raw_affiliation_string":"Center for Embedded Computer Systems, University of California, Irvine. bgorjiar@cecs.uci.edu","institution_ids":["https://openalex.org/I204250578"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5104058284","display_name":"Mehrdad Reshadi","orcid":null},"institutions":[{"id":"https://openalex.org/I204250578","display_name":"University of California, Irvine","ror":"https://ror.org/04gyf1771","country_code":"US","type":"education","lineage":["https://openalex.org/I204250578"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mehrdad Reshadi","raw_affiliation_strings":["Center for Embedded Computer Systems, University of California, Irvine, USA","Center for Embedded Computer Systems, University of California, Irvine. reshadi@cecs.uci.edu"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Center for Embedded Computer Systems, University of California, Irvine, USA","institution_ids":["https://openalex.org/I204250578"]},{"raw_affiliation_string":"Center for Embedded Computer Systems, University of California, Irvine. reshadi@cecs.uci.edu","institution_ids":["https://openalex.org/I204250578"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5025797692","display_name":"Daniel D. Gajski","orcid":null},"institutions":[{"id":"https://openalex.org/I204250578","display_name":"University of California, Irvine","ror":"https://ror.org/04gyf1771","country_code":"US","type":"education","lineage":["https://openalex.org/I204250578"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Daniel Gajski","raw_affiliation_strings":["Center for Embedded Computer Systems, University of California, Irvine, USA","Center for Embedded Computer Systems, University of California, Irvine. gajski@cecs.uci.edu"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Center for Embedded Computer Systems, University of California, Irvine, USA","institution_ids":["https://openalex.org/I204250578"]},{"raw_affiliation_string":"Center for Embedded Computer Systems, University of California, Irvine. gajski@cecs.uci.edu","institution_ids":["https://openalex.org/I204250578"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I204250578"],"apc_list":null,"apc_paid":null,"fwci":1.1159,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.74824139,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"356","last_page":"361"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.9116718769073486},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8429301977157593},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.653775691986084},{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.6347640156745911},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5855398178100586},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5847095847129822},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5359903573989868},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.5082066059112549},{"id":"https://openalex.org/keywords/predictability","display_name":"Predictability","score":0.48095718026161194},{"id":"https://openalex.org/keywords/time-to-market","display_name":"Time to market","score":0.4612177312374115},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.4586091637611389},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.44031861424446106},{"id":"https://openalex.org/keywords/processor-design","display_name":"Processor design","score":0.4125516414642334},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.22301891446113586},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.2171766459941864}],"concepts":[{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.9116718769073486},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8429301977157593},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.653775691986084},{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.6347640156745911},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5855398178100586},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5847095847129822},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5359903573989868},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.5082066059112549},{"id":"https://openalex.org/C197640229","wikidata":"https://www.wikidata.org/wiki/Q2534066","display_name":"Predictability","level":2,"score":0.48095718026161194},{"id":"https://openalex.org/C2779229675","wikidata":"https://www.wikidata.org/wiki/Q445235","display_name":"Time to market","level":2,"score":0.4612177312374115},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.4586091637611389},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.44031861424446106},{"id":"https://openalex.org/C526435321","wikidata":"https://www.wikidata.org/wiki/Q1303814","display_name":"Processor design","level":2,"score":0.4125516414642334},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.22301891446113586},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.2171766459941864},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccd.2006.4380841","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2006.4380841","pdf_url":null,"source":{"id":"https://openalex.org/S4210174938","display_name":"Proceedings, IEEE International Conference on Computer Design/Proceedings - IEEE International Conference on Computer Design","issn_l":"1063-6404","issn":["1063-6404","2576-6996"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 International Conference on Computer Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Decent work and economic growth","score":0.4399999976158142,"id":"https://metadata.un.org/sdg/8"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1954375898","https://openalex.org/W1992857325","https://openalex.org/W1998849536","https://openalex.org/W2007894850","https://openalex.org/W2111330410","https://openalex.org/W2115541788","https://openalex.org/W2137006143","https://openalex.org/W2138098630","https://openalex.org/W2138362897","https://openalex.org/W2160507484","https://openalex.org/W2347056315","https://openalex.org/W2402419031","https://openalex.org/W4249267688"],"related_works":["https://openalex.org/W2111251553","https://openalex.org/W3148693912","https://openalex.org/W2120549874","https://openalex.org/W2156069452","https://openalex.org/W4210841712","https://openalex.org/W2045146060","https://openalex.org/W2543290882","https://openalex.org/W2166021916","https://openalex.org/W1903431847","https://openalex.org/W4235515009"],"abstract_inverted_index":{"Constraints":[0],"of":[1,12,81,132,138,146],"embedded":[2],"systems":[3],"and":[4,15,33,53,108,135,156,183],"the":[5,10,27,43,54,71,79,82,95,126,130,133,136,139,165],"shrinking":[6],"time-to-market":[7],"have":[8,104,169],"elevated":[9],"importance":[11],"designer":[13,72],"productivity":[14],"design":[16,41,66,92],"predictability":[17,67],"more":[18],"than":[19,149],"ever.":[20],"To":[21],"improve":[22],"productivity,":[23],"in":[24,47,63,115,188],"ASIP":[25,40],"approaches":[26,65],"system":[28],"is":[29,45,56,68,113,123,143],"designed":[30],"with":[31,152],"software":[32],"executed":[34],"on":[35],"a":[36,90,116,172],"customized":[37],"processor.":[38],"In":[39,85],"flow,":[42],"processor":[44,97],"described":[46,114,187],"an":[48,144],"Architecture":[49],"Description":[50],"Language":[51],"(ADL)":[52],"toolset":[55,127],"generated":[57],"from":[58],"that":[59,163,179],"ADL":[60],"automatically.":[61],"However,":[62],"these":[64],"low":[69],"because":[70],"has":[73],"little":[74],"or":[75,98],"no":[76],"control":[77],"over":[78],"quality":[80],"final":[83],"implementation.":[84],"this":[86],"paper,":[87],"we":[88],"present":[89],"new":[91,185],"approach":[93],"where":[94],"target":[96],"Intellectual":[99],"Property":[100],"(IP)":[101],"does":[102],"not":[103],"any":[105,160],"predefined":[106],"instruction-set":[107],"its":[109],"datapath":[110],"component":[111],"netlist":[112],"Generic":[117],"Netlist":[118],"Representation":[119],"(GNR).":[120],"The":[121,141],"GNR":[122,142],"used":[124],"by":[125],"to":[128],"generate":[129],"controller":[131],"IP":[134],"RTL":[137,153],"design.":[140],"order":[145],"magnitude":[147],"shorter":[148],"state-of-the-art":[150],"ADLs":[151],"generation":[154],"capabilities":[155],"yet":[157],"can":[158,181],"capture":[159],"structural":[161],"details":[162],"affect":[164],"implementation":[166],"quality.":[167],"We":[168],"also":[170],"developed":[171],"web-based":[173],"interface":[174],"for":[175],"our":[176],"toolset,":[177],"so":[178],"users":[180],"upload":[182],"evaluate":[184],"IPs":[186],"GNR.":[189]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
