{"id":"https://openalex.org/W2042249682","doi":"https://doi.org/10.1109/iccd.2006.4380818","title":"An Enhancement for a Scheduling Logic Pipelined over two Cycles","display_name":"An Enhancement for a Scheduling Logic Pipelined over two Cycles","publication_year":2006,"publication_date":"2006-10-01","ids":{"openalex":"https://openalex.org/W2042249682","doi":"https://doi.org/10.1109/iccd.2006.4380818","mag":"2042249682"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.2006.4380818","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2006.4380818","pdf_url":null,"source":{"id":"https://openalex.org/S4210174938","display_name":"Proceedings, IEEE International Conference on Computer Design/Proceedings - IEEE International Conference on Computer Design","issn_l":"1063-6404","issn":["1063-6404","2576-6996"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 International Conference on Computer Design","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5035870105","display_name":"Rub\u00e9n Gran Tejero","orcid":"https://orcid.org/0000-0002-4031-5651"},"institutions":[{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Ruben Gran","raw_affiliation_strings":["Departamento de Arquitectura de Computadores, Universidad Polit\u00e9cnica de Catalunya, Spain","Departamento de Arquitectura de Computadores. Universidad Polit\u00e9cnica de Catalu\u00f1a. rgran@ac.upc.edu"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Departamento de Arquitectura de Computadores, Universidad Polit\u00e9cnica de Catalunya, Spain","institution_ids":["https://openalex.org/I9617848"]},{"raw_affiliation_string":"Departamento de Arquitectura de Computadores. Universidad Polit\u00e9cnica de Catalu\u00f1a. rgran@ac.upc.edu","institution_ids":["https://openalex.org/I9617848"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000717476","display_name":"Enric Morancho","orcid":"https://orcid.org/0000-0003-2403-8145"},"institutions":[{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Enric Morancho","raw_affiliation_strings":["Departamento de Arquitectura de Computadores, Universidad Polit\u00e9cnica de Catalunya, Spain","Departamento de Arquitectura de Computadores. Universidad Polit\u00e9cnica de Catalu\u00f1a. enricm@ac.upc.edu"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Departamento de Arquitectura de Computadores, Universidad Polit\u00e9cnica de Catalunya, Spain","institution_ids":["https://openalex.org/I9617848"]},{"raw_affiliation_string":"Departamento de Arquitectura de Computadores. Universidad Polit\u00e9cnica de Catalu\u00f1a. enricm@ac.upc.edu","institution_ids":["https://openalex.org/I9617848"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5021038520","display_name":"\u00c0ngel Oliv\u00e9","orcid":null},"institutions":[{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Angel Olive","raw_affiliation_strings":["Departamento de Arquitectura de Computadores, Universidad Polit\u00e9cnica de Catalunya, Spain","Departamento de Arquitectura de Computadores. Universidad Polit\u00e9cnica de Catalu\u00f1a. angel@ac.upc.edu"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Departamento de Arquitectura de Computadores, Universidad Polit\u00e9cnica de Catalunya, Spain","institution_ids":["https://openalex.org/I9617848"]},{"raw_affiliation_string":"Departamento de Arquitectura de Computadores. Universidad Polit\u00e9cnica de Catalu\u00f1a. angel@ac.upc.edu","institution_ids":["https://openalex.org/I9617848"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5028457566","display_name":"J.M. Llaberia","orcid":"https://orcid.org/0000-0002-3753-4108"},"institutions":[{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Jose M. Llaberia","raw_affiliation_strings":["Departamento de Arquitectura de Computadores, Universidad Polit\u00e9cnica de Catalunya, Spain","Departamento de Arquitectura de Computadores. Universidad Polit\u00e9cnica de Catalu\u00f1a. llaberia@ac.upc.edu"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Departamento de Arquitectura de Computadores, Universidad Polit\u00e9cnica de Catalunya, Spain","institution_ids":["https://openalex.org/I9617848"]},{"raw_affiliation_string":"Departamento de Arquitectura de Computadores. Universidad Polit\u00e9cnica de Catalu\u00f1a. llaberia@ac.upc.edu","institution_ids":["https://openalex.org/I9617848"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I9617848"],"apc_list":null,"apc_paid":null,"fwci":0.4464,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.52943354,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"203","last_page":"209"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8464044332504272},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.629128634929657},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.6288700103759766},{"id":"https://openalex.org/keywords/dynamic-priority-scheduling","display_name":"Dynamic priority scheduling","score":0.532729983329773},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5316413640975952},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.47795701026916504},{"id":"https://openalex.org/keywords/processor-scheduling","display_name":"Processor scheduling","score":0.4374939799308777},{"id":"https://openalex.org/keywords/spec#","display_name":"Spec#","score":0.41389167308807373},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.32485175132751465},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.15108808875083923},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.12867531180381775},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.11542275547981262},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.08072775602340698}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8464044332504272},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.629128634929657},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.6288700103759766},{"id":"https://openalex.org/C107568181","wikidata":"https://www.wikidata.org/wiki/Q5319000","display_name":"Dynamic priority scheduling","level":3,"score":0.532729983329773},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5316413640975952},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.47795701026916504},{"id":"https://openalex.org/C2984822820","wikidata":"https://www.wikidata.org/wiki/Q1123036","display_name":"Processor scheduling","level":3,"score":0.4374939799308777},{"id":"https://openalex.org/C2778565505","wikidata":"https://www.wikidata.org/wiki/Q2207566","display_name":"Spec#","level":2,"score":0.41389167308807373},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.32485175132751465},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.15108808875083923},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.12867531180381775},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.11542275547981262},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.08072775602340698},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/iccd.2006.4380818","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2006.4380818","pdf_url":null,"source":{"id":"https://openalex.org/S4210174938","display_name":"Proceedings, IEEE International Conference on Computer Design/Proceedings - IEEE International Conference on Computer Design","issn_l":"1063-6404","issn":["1063-6404","2576-6996"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 International Conference on Computer Design","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.102.7575","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.102.7575","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://personals.ac.upc.edu/enricm/Pubs/iccd06.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.559.7310","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.559.7310","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://personales.ac.upc.edu/enricm/Pubs/jp06.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":31,"referenced_works":["https://openalex.org/W146413762","https://openalex.org/W1584321010","https://openalex.org/W1987674899","https://openalex.org/W2032094184","https://openalex.org/W2039631685","https://openalex.org/W2112802341","https://openalex.org/W2112841617","https://openalex.org/W2121539621","https://openalex.org/W2123413169","https://openalex.org/W2125114475","https://openalex.org/W2130124967","https://openalex.org/W2130766965","https://openalex.org/W2131556574","https://openalex.org/W2140782438","https://openalex.org/W2148570943","https://openalex.org/W2153456949","https://openalex.org/W2156263417","https://openalex.org/W2157676568","https://openalex.org/W2164376452","https://openalex.org/W2535965777","https://openalex.org/W2537134123","https://openalex.org/W4206262716","https://openalex.org/W4230658192","https://openalex.org/W4237273530","https://openalex.org/W4240643561","https://openalex.org/W4250273581","https://openalex.org/W4251451722","https://openalex.org/W4254003710","https://openalex.org/W6634836887","https://openalex.org/W6679595550","https://openalex.org/W6684386307"],"related_works":["https://openalex.org/W878150521","https://openalex.org/W2008941207","https://openalex.org/W2373662841","https://openalex.org/W17155033","https://openalex.org/W1970478390","https://openalex.org/W3207760230","https://openalex.org/W1496222301","https://openalex.org/W1533638723","https://openalex.org/W1781596060","https://openalex.org/W2151588880"],"abstract_inverted_index":{"Out":[0],"of":[1,105,113,140,171,180],"order":[2],"processors":[3],"use":[4],"the":[5,21,37,110,128,138],"dynamic":[6],"scheduling":[7,38,65,77,139],"logic":[8,18,39,78],"both":[9],"to":[10,13,23,62,126],"expose":[11],"and":[12,178],"exploit":[14],"parallelism.":[15],"Pipelining":[16],"this":[17,68],"may":[19],"sacrifice":[20],"ability":[22],"execute":[24],"dependent":[25,141],"instructions":[26,90,96,114,142],"in":[27,47,87,119,143,148],"consecutive":[28,144],"cycles.":[29,82,145],"Several":[30],"previous":[31],"studies":[32],"have":[33,107],"shown":[34],"that":[35,97,153],"pipelining":[36],"over":[40,80],"two":[41,72,81,155,164],"cycles":[42],"degrades":[43],"performance;":[44],"our":[45,154,172],"evaluations,":[46],"a":[48,56,76,149,176],"4-way":[49,150],"machine,":[50],"on":[51,159],"SPEC-2000":[52],"integer":[53],"benchmarks":[54],"show":[55,152],"performance":[57,170],"degradation":[58],"about":[59],"11%":[60],"compared":[61],"an":[63,181],"unpipelined":[64,182],"logic.":[66],"In":[67],"work,":[69],"we":[70],"present":[71],"non-speculative":[73],"enhancements":[74,157],"for":[75,101,117],"pipelined":[79],"The":[83,122,169],"idea":[84],"is":[85,125,135,174],"computing":[86],"advance":[88],"which":[89],"will":[91],"be":[92],"woken-up":[93],"by":[94],"all":[95,104],"are":[98],"currently":[99],"competing":[100],"selection.":[102],"Once":[103],"them":[106],"been":[108],"selected,":[109],"pre-computed":[111],"group":[112],"can":[115],"compete":[116],"selection":[118],"next":[120],"cycle.":[121],"enhancement":[123],"goal":[124],"tolerate":[127],"scheduling-loop":[129],"latency":[130],"when":[131],"not":[132],"enough":[133],"ILP":[134],"available":[136],"through":[137],"Our":[146],"results":[147],"machine":[151],"proposed":[156,166],"perform,":[158],"average,":[160],"slightly":[161],"better":[162],"than":[163],"previously":[165],"speculative":[167],"schedulers.":[168],"proposals":[173],"within":[175],"2.6%":[177],"2%":[179],"ideal":[183],"scheduler.":[184]},"counts_by_year":[{"year":2013,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
