{"id":"https://openalex.org/W2121865749","doi":"https://doi.org/10.1109/iccd.2006.4380812","title":"Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles","display_name":"Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles","publication_year":2006,"publication_date":"2006-10-01","ids":{"openalex":"https://openalex.org/W2121865749","doi":"https://doi.org/10.1109/iccd.2006.4380812","mag":"2121865749"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.2006.4380812","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2006.4380812","pdf_url":null,"source":{"id":"https://openalex.org/S4210174938","display_name":"Proceedings, IEEE International Conference on Computer Design/Proceedings - IEEE International Conference on Computer Design","issn_l":"1063-6404","issn":["1063-6404","2576-6996"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 International Conference on Computer Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109151274","display_name":"Zhiyi Yu","orcid":null},"institutions":[{"id":"https://openalex.org/I84218800","display_name":"University of California, Davis","ror":"https://ror.org/05rrcem69","country_code":"US","type":"education","lineage":["https://openalex.org/I84218800"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Zhiyi Yu","raw_affiliation_strings":["ECE Department, University of California, Davis, USA","ECE Department, University of California Davis"],"affiliations":[{"raw_affiliation_string":"ECE Department, University of California, Davis, USA","institution_ids":["https://openalex.org/I84218800"]},{"raw_affiliation_string":"ECE Department, University of California Davis","institution_ids":["https://openalex.org/I84218800"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5058921665","display_name":"Bevan Baas","orcid":null},"institutions":[{"id":"https://openalex.org/I84218800","display_name":"University of California, Davis","ror":"https://ror.org/05rrcem69","country_code":"US","type":"education","lineage":["https://openalex.org/I84218800"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Bevan Baas","raw_affiliation_strings":["ECE Department, University of California, Davis, USA","ECE Department, University of California Davis"],"affiliations":[{"raw_affiliation_string":"ECE Department, University of California, Davis, USA","institution_ids":["https://openalex.org/I84218800"]},{"raw_affiliation_string":"ECE Department, University of California Davis","institution_ids":["https://openalex.org/I84218800"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5109151274"],"corresponding_institution_ids":["https://openalex.org/I84218800"],"apc_list":null,"apc_paid":null,"fwci":2.6181,"has_fulltext":false,"cited_by_count":29,"citation_normalized_percentile":{"value":0.90242442,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"174","last_page":"179"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12162","display_name":"Cellular Automata and Applications","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.837092399597168},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.7907679080963135},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.7401593327522278},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.7036614418029785},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.699282705783844},{"id":"https://openalex.org/keywords/robustness","display_name":"Robustness (evolution)","score":0.6520856618881226},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.6303418874740601},{"id":"https://openalex.org/keywords/tile","display_name":"Tile","score":0.5885787606239319},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5751981735229492},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5342418551445007},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5045443773269653},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.36255013942718506},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.10168591141700745},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.06949028372764587},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.06630080938339233}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.837092399597168},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.7907679080963135},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.7401593327522278},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.7036614418029785},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.699282705783844},{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.6520856618881226},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.6303418874740601},{"id":"https://openalex.org/C2780728851","wikidata":"https://www.wikidata.org/wiki/Q468402","display_name":"Tile","level":2,"score":0.5885787606239319},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5751981735229492},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5342418551445007},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5045443773269653},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.36255013942718506},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.10168591141700745},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.06949028372764587},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.06630080938339233},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccd.2006.4380812","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2006.4380812","pdf_url":null,"source":{"id":"https://openalex.org/S4210174938","display_name":"Proceedings, IEEE International Conference on Computer Design/Proceedings - IEEE International Conference on Computer Design","issn_l":"1063-6404","issn":["1063-6404","2576-6996"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 International Conference on Computer Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W97427664","https://openalex.org/W1541688521","https://openalex.org/W1575732703","https://openalex.org/W1594986119","https://openalex.org/W2005345974","https://openalex.org/W2108730429","https://openalex.org/W2117648153","https://openalex.org/W2118580195","https://openalex.org/W2143626656","https://openalex.org/W2152484003","https://openalex.org/W2157024459","https://openalex.org/W2169049905","https://openalex.org/W3103339143","https://openalex.org/W4233874538","https://openalex.org/W4245052796","https://openalex.org/W4245348408","https://openalex.org/W4285719527","https://openalex.org/W6651790823","https://openalex.org/W6677845609","https://openalex.org/W6684687133","https://openalex.org/W6813828836"],"related_works":["https://openalex.org/W4294338060","https://openalex.org/W1491017262","https://openalex.org/W1494824878","https://openalex.org/W4297819361","https://openalex.org/W2388040150","https://openalex.org/W4237360612","https://openalex.org/W4230718388","https://openalex.org/W2002682434","https://openalex.org/W2102117846","https://openalex.org/W2481546399"],"abstract_inverted_index":{"This":[0],"paper":[1],"investigates":[2],"implementation":[3],"techniques":[4],"for":[5,55,61],"tile-based":[6,90],"chip":[7],"multiprocessors":[8],"with":[9],"Globally":[10],"Asynchronous":[11],"Locally":[12],"Synchronous":[13],"(GALS)":[14],"clocking":[15],"styles.":[16],"These":[17],"architectures":[18],"can":[19],"simplify":[20],"the":[21],"physical":[22,52],"design":[23,53,77],"flow":[24,54],"since":[25],"they":[26,39],"allow":[27],"focusing":[28],"on":[29],"a":[30,51,76,83],"single":[31],"processor":[32],"when":[33],"designing":[34],"an":[35],"entire":[36],"chip.":[37],"However,":[38],"also":[40],"introduce":[41],"challenges":[42],"to":[43,67],"maintain":[44],"system":[45],"robustness":[46],"and":[47,64],"scalability.":[48,74],"We":[49],"propose":[50,65],"these":[56],"architectures,":[57],"investigate":[58],"timing":[59],"issues":[60],"robust":[62],"implementations,":[63],"methods":[66],"take":[68],"full":[69],"advantage":[70],"of":[71],"their":[72],"potential":[73],"As":[75],"example,":[78],"we":[79],"present":[80],"data":[81],"from":[82],"recently":[84],"implemented":[85],"single-chip":[86],"6":[87,89],"x":[88],"GALS":[91],"processing":[92],"array.":[93]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2022,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}