{"id":"https://openalex.org/W2100006166","doi":"https://doi.org/10.1109/iccd.2006.4380807","title":"A Performance and Power Analysis of WK-Recursive and Mesh Networks for Network-on-Chips","display_name":"A Performance and Power Analysis of WK-Recursive and Mesh Networks for Network-on-Chips","publication_year":2006,"publication_date":"2006-10-01","ids":{"openalex":"https://openalex.org/W2100006166","doi":"https://doi.org/10.1109/iccd.2006.4380807","mag":"2100006166"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.2006.4380807","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2006.4380807","pdf_url":null,"source":{"id":"https://openalex.org/S4210174938","display_name":"Proceedings, IEEE International Conference on Computer Design/Proceedings - IEEE International Conference on Computer Design","issn_l":"1063-6404","issn":["1063-6404","2576-6996"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 International Conference on Computer Design","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5043762973","display_name":"Dara Rahmati","orcid":"https://orcid.org/0000-0003-0104-4016"},"institutions":[{"id":"https://openalex.org/I133529467","display_name":"Sharif University of Technology","ror":"https://ror.org/024c2fq17","country_code":"IR","type":"education","lineage":["https://openalex.org/I133529467"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"D. Rahmati","raw_affiliation_strings":["Department of Computer Engineering, Sharif University of Technology, Tehran, Iran"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Sharif University of Technology, Tehran, Iran","institution_ids":["https://openalex.org/I133529467"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5029507843","display_name":"Abbas Eslami Kiasari","orcid":null},"institutions":[{"id":"https://openalex.org/I133529467","display_name":"Sharif University of Technology","ror":"https://ror.org/024c2fq17","country_code":"IR","type":"education","lineage":["https://openalex.org/I133529467"]},{"id":"https://openalex.org/I3145578848","display_name":"Institute for Cognitive Science Studies","ror":"https://ror.org/0378cd528","country_code":"IR","type":"facility","lineage":["https://openalex.org/I3145578848"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"A. E. Kiasari","raw_affiliation_strings":["Department of Computer Engineering, Sharif University of Technology, Tehran, Iran","School of Computer Science, Institute of Studies in Theoretical Physics and Mathematics, Tehran, Iran"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Sharif University of Technology, Tehran, Iran","institution_ids":["https://openalex.org/I133529467"]},{"raw_affiliation_string":"School of Computer Science, Institute of Studies in Theoretical Physics and Mathematics, Tehran, Iran","institution_ids":["https://openalex.org/I3145578848"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091774451","display_name":"Shaahin Hessabi","orcid":"https://orcid.org/0000-0003-3193-2567"},"institutions":[{"id":"https://openalex.org/I133529467","display_name":"Sharif University of Technology","ror":"https://ror.org/024c2fq17","country_code":"IR","type":"education","lineage":["https://openalex.org/I133529467"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"S. Hessabi","raw_affiliation_strings":["Department of Computer Engineering, Sharif University of Technology, Tehran, Iran"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Sharif University of Technology, Tehran, Iran","institution_ids":["https://openalex.org/I133529467"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5040238844","display_name":"Hamid Sarbazi\u2010Azad","orcid":"https://orcid.org/0000-0003-4079-8603"},"institutions":[{"id":"https://openalex.org/I133529467","display_name":"Sharif University of Technology","ror":"https://ror.org/024c2fq17","country_code":"IR","type":"education","lineage":["https://openalex.org/I133529467"]},{"id":"https://openalex.org/I3145578848","display_name":"Institute for Cognitive Science Studies","ror":"https://ror.org/0378cd528","country_code":"IR","type":"facility","lineage":["https://openalex.org/I3145578848"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"H. Sarbazi-Azad","raw_affiliation_strings":["Department of Computer Engineering, Sharif University of Technology, Tehran, Iran","School of Computer Science, Institute of Studies in Theoretical Physics and Mathematics, Tehran, Iran"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Sharif University of Technology, Tehran, Iran","institution_ids":["https://openalex.org/I133529467"]},{"raw_affiliation_string":"School of Computer Science, Institute of Studies in Theoretical Physics and Mathematics, Tehran, Iran","institution_ids":["https://openalex.org/I3145578848"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":29,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"142","last_page":"147"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10179","display_name":"Supercapacitor Materials and Fabrication","score":0.9939000010490417,"subfield":{"id":"https://openalex.org/subfields/2504","display_name":"Electronic, Optical and Magnetic Materials"},"field":{"id":"https://openalex.org/fields/25","display_name":"Materials Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9921000003814697,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.8169878721237183},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.7490004301071167},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7166666984558105},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.6990810632705688},{"id":"https://openalex.org/keywords/mesh-networking","display_name":"Mesh networking","score":0.609895646572113},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.567583441734314},{"id":"https://openalex.org/keywords/modularity","display_name":"Modularity (biology)","score":0.5627245306968689},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.5281063318252563},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.5053456425666809},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.45776063203811646},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4527979791164398},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4436338543891907},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.40462759137153625},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3975027799606323},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.39599496126174927},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.34805887937545776},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.24041029810905457},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.2262701690196991},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14937996864318848},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.06949397921562195},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.06771695613861084}],"concepts":[{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.8169878721237183},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.7490004301071167},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7166666984558105},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.6990810632705688},{"id":"https://openalex.org/C123691950","wikidata":"https://www.wikidata.org/wiki/Q25552104","display_name":"Mesh networking","level":3,"score":0.609895646572113},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.567583441734314},{"id":"https://openalex.org/C2779478453","wikidata":"https://www.wikidata.org/wiki/Q6889748","display_name":"Modularity (biology)","level":2,"score":0.5627245306968689},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.5281063318252563},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.5053456425666809},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.45776063203811646},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4527979791164398},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4436338543891907},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.40462759137153625},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3975027799606323},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.39599496126174927},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.34805887937545776},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.24041029810905457},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.2262701690196991},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14937996864318848},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.06949397921562195},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.06771695613861084},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C54355233","wikidata":"https://www.wikidata.org/wiki/Q7162","display_name":"Genetics","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iccd.2006.4380807","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2006.4380807","pdf_url":null,"source":{"id":"https://openalex.org/S4210174938","display_name":"Proceedings, IEEE International Conference on Computer Design/Proceedings - IEEE International Conference on Computer Design","issn_l":"1063-6404","issn":["1063-6404","2576-6996"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 International Conference on Computer Design","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.259.4925","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.259.4925","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cecs.uci.edu/%7Epapers/iccd2006/papers/paper_213.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8500000238418579,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1869683263","https://openalex.org/W2032915955","https://openalex.org/W2097565437","https://openalex.org/W2111553220","https://openalex.org/W2130183852","https://openalex.org/W2138444824","https://openalex.org/W2156677140","https://openalex.org/W4235172414"],"related_works":["https://openalex.org/W2121335669","https://openalex.org/W2135981148","https://openalex.org/W2150291485","https://openalex.org/W2388672758","https://openalex.org/W2024473227","https://openalex.org/W2065289416","https://openalex.org/W2754086592","https://openalex.org/W2069618434","https://openalex.org/W2144357574","https://openalex.org/W4230458348"],"abstract_inverted_index":{"Network-on-chip":[0],"(NoC)":[1],"has":[2],"been":[3],"proposed":[4],"as":[5,60],"an":[6],"attractive":[7],"alternative":[8],"to":[9,13,57],"traditional":[10],"dedicated":[11],"wires":[12],"achieve":[14],"high":[15,94],"performance":[16],"and":[17,43,74,77,104],"modularity.":[18],"Power":[19],"efficiency":[20],"is":[21,37,113],"one":[22],"of":[23,34,53,72,110,117],"the":[24,51,54,61,79,107,118],"most":[25],"important":[26,38],"concerns":[27],"in":[28,39,64,93],"NoC":[29],"architecture":[30],"design.":[31],"The":[32],"choice":[33],"network":[35],"topology":[36,63,112],"designing":[40],"a":[41,90,122],"low-power":[42],"high-performance":[44],"NoC.":[45,65],"In":[46],"this":[47],"paper,":[48],"we":[49],"propose":[50,89],"use":[52],"WK-recursive":[55,75,111],"networks":[56],"be":[58],"used":[59],"underlying":[62],"We":[66,87],"have":[67],"implemented":[68],"VHDL":[69],"hardware":[70],"model":[71],"mesh":[73,120],"topologies":[76,103],"measured":[78],"latency":[80,100],"results":[81],"using":[82],"simulation":[83],"with":[84],"these":[85,102],"implementation.":[86],"also":[88],"novel":[91],"approach":[92],"level":[95],"power":[96,108],"modeling":[97],"based":[98],"on":[99,121],"for":[101],"show":[105],"that":[106,116],"consumption":[109],"less":[114],"than":[115],"equivalent":[119],"chip.":[123]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":5}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}