{"id":"https://openalex.org/W1550899637","doi":"https://doi.org/10.1109/iccd.2004.1347947","title":"A minimal dual-core speculative multi-threading architecture","display_name":"A minimal dual-core speculative multi-threading architecture","publication_year":2004,"publication_date":"2004-11-08","ids":{"openalex":"https://openalex.org/W1550899637","doi":"https://doi.org/10.1109/iccd.2004.1347947","mag":"1550899637"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.2004.1347947","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2004.1347947","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings.","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5069298429","display_name":"Srikanth T. Srinivasan","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S.T. Srinivasan","raw_affiliation_strings":["Microarchitecture Research Laboratory, Intel Corporation, USA","Microarchit. Res. Lab., Intel Corp., USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microarchitecture Research Laboratory, Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Microarchit. Res. Lab., Intel Corp., USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065922595","display_name":"Haitham Akkary","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"H. Akkary","raw_affiliation_strings":["Microarchitecture Research Laboratory, Intel Corporation, USA","Microarchit. Res. Lab., Intel Corp., USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microarchitecture Research Laboratory, Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Microarchit. Res. Lab., Intel Corp., USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5046180885","display_name":"Thomas J. Holman","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"T. Holman","raw_affiliation_strings":["Microarchitecture Research Laboratory, Intel Corporation, USA","Microarchit. Res. Lab., Intel Corp., USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microarchitecture Research Laboratory, Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Microarchit. Res. Lab., Intel Corp., USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109211542","display_name":"Konrad Lai","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Konrad Lai","raw_affiliation_strings":["Microarchitecture Research Laboratory, Intel Corporation, USA","Microarchit. Res. Lab., Intel Corp., USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microarchitecture Research Laboratory, Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Microarchit. Res. Lab., Intel Corp., USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":1.03,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.71444469,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"45","issue":null,"first_page":"360","last_page":"367"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10772","display_name":"Distributed systems and fault tolerance","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/thread","display_name":"Thread (computing)","score":0.7470197081565857},{"id":"https://openalex.org/keywords/spec#","display_name":"Spec#","score":0.7090671062469482},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.48223504424095154},{"id":"https://openalex.org/keywords/speculative-multithreading","display_name":"Speculative multithreading","score":0.47921687364578247},{"id":"https://openalex.org/keywords/speculative-execution","display_name":"Speculative execution","score":0.46784719824790955},{"id":"https://openalex.org/keywords/threading","display_name":"Threading (protein sequence)","score":0.4392319321632385},{"id":"https://openalex.org/keywords/multithreading","display_name":"Multithreading","score":0.3970474600791931},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3686813712120056},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3107399344444275},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.24859994649887085}],"concepts":[{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.7470197081565857},{"id":"https://openalex.org/C2778565505","wikidata":"https://www.wikidata.org/wiki/Q2207566","display_name":"Spec#","level":2,"score":0.7090671062469482},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.48223504424095154},{"id":"https://openalex.org/C15296174","wikidata":"https://www.wikidata.org/wiki/Q7575343","display_name":"Speculative multithreading","level":4,"score":0.47921687364578247},{"id":"https://openalex.org/C141331961","wikidata":"https://www.wikidata.org/wiki/Q2164465","display_name":"Speculative execution","level":2,"score":0.46784719824790955},{"id":"https://openalex.org/C200307862","wikidata":"https://www.wikidata.org/wiki/Q7797175","display_name":"Threading (protein sequence)","level":3,"score":0.4392319321632385},{"id":"https://openalex.org/C201410400","wikidata":"https://www.wikidata.org/wiki/Q1064412","display_name":"Multithreading","level":3,"score":0.3970474600791931},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3686813712120056},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3107399344444275},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.24859994649887085},{"id":"https://openalex.org/C47701112","wikidata":"https://www.wikidata.org/wiki/Q735188","display_name":"Protein structure","level":2,"score":0.0},{"id":"https://openalex.org/C46141821","wikidata":"https://www.wikidata.org/wiki/Q209402","display_name":"Nuclear magnetic resonance","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iccd.2004.1347947","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2004.1347947","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings.","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.553.1292","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.553.1292","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://iccd.et.tudelft.nl/Proceedings/2004/22310360.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Peace, Justice and strong institutions","score":0.4300000071525574,"id":"https://metadata.un.org/sdg/16"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W63944998","https://openalex.org/W277936934","https://openalex.org/W1596644655","https://openalex.org/W1828727480","https://openalex.org/W1976058961","https://openalex.org/W2019674193","https://openalex.org/W2040701288","https://openalex.org/W2095703459","https://openalex.org/W2097230158","https://openalex.org/W2103224933","https://openalex.org/W2109440006","https://openalex.org/W2117515905","https://openalex.org/W2122059338","https://openalex.org/W2123608497","https://openalex.org/W2146173591","https://openalex.org/W2162523628","https://openalex.org/W2164393230","https://openalex.org/W2983076786","https://openalex.org/W4232096869","https://openalex.org/W4235677263","https://openalex.org/W4242484660","https://openalex.org/W4245971498","https://openalex.org/W6602613798","https://openalex.org/W6635798368"],"related_works":["https://openalex.org/W2371844484","https://openalex.org/W2765149243","https://openalex.org/W2650626006","https://openalex.org/W2124997519","https://openalex.org/W2543764088","https://openalex.org/W1576844086","https://openalex.org/W2099709763","https://openalex.org/W4244698026","https://openalex.org/W2122863560","https://openalex.org/W2000490092"],"abstract_inverted_index":{"Speculative":[0],"multi-threading":[1],"(SpMT)":[2],"can":[3,82],"improve":[4],"single-threaded":[5,35],"application":[6],"performance":[7,120,148,166],"using":[8,37],"the":[9,58,65,71,114,155,165,197],"multiple":[10],"thread":[11,27,78,116],"contexts":[12],"available":[13],"in":[14,86,110],"current":[15],"processors.":[16],"We":[17,68],"propose":[18],"a":[19,38,51,111,133],"minimal":[20],"SpMT":[21,77,130,158,170,190],"model":[22,30,131],"that":[23,81,136],"uses":[24],"only":[25],"two":[26],"contexts.":[28],"The":[29],"achieves":[31],"significant":[32],"speedups":[33],"for":[34,41],"applications":[36],"low-overhead":[39],"scheme":[40],"detecting":[42],"and":[43,50,94,99,125,179,184],"selectively":[44],"recovering":[45],"from":[46,172,176,181],"data":[47],"dependence":[48],"violations,":[49],"novel":[52],"wrong":[53,66],"path":[54],"predictor":[55],"to":[56,104,169,195],"reduce":[57],"number":[59],"of":[60,122,150,157,164,189,200],"speculative":[61],"threads":[62],"executing":[63],"along":[64],"path.":[67],"also":[69],"study":[70],"interactions":[72],"between":[73],"three":[74,107,143,187],"previously":[75],"proposed":[76],"spawning":[79,117],"policies":[80,97,108,118,144],"be":[83,193],"implemented":[84],"dynamically":[85],"hardware":[87],"-":[88,98,160],"Fork":[89],"on":[90,128,161],"Call,":[91],"Loop":[92],"Continuation":[93],"Run":[95],"Ahead":[96],"show":[100,119,185],"it":[101],"is":[102],"beneficial":[103],"implement":[105],"all":[106,142,186],"together":[109],"processor.":[112],"While":[113],"individual":[115],"benefits":[121,159,167,191],"14%,":[123],"5%":[124],"4%":[126],"respectively":[127],"our":[129],"over":[132],"base":[134],"processor":[135],"does":[137],"not":[138],"exploit":[139],"SpMT,":[140],"combining":[141],"shows":[145],"an":[146],"average":[147],"gain":[149],"20%.":[151],"Finally,":[152],"we":[153],"identify":[154],"sources":[156,188],"average,":[162],"58%":[163],"due":[168],"comes":[171],"cache":[173],"prefetching,":[174],"33%":[175],"instruction":[177],"reuse,":[178],"9%":[180],"branch":[182],"precomputation":[183],"must":[192],"utilized":[194],"realize":[196],"full":[198],"potential":[199],"SpMT.":[201]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
