{"id":"https://openalex.org/W4247367638","doi":"https://doi.org/10.1109/iccd.2003.1240952","title":"Xpipes: a latency insensitive parameterized network-on-chip architecture for multiprocessor SoCs","display_name":"Xpipes: a latency insensitive parameterized network-on-chip architecture for multiprocessor SoCs","publication_year":2004,"publication_date":"2004-05-06","ids":{"openalex":"https://openalex.org/W4247367638","doi":"https://doi.org/10.1109/iccd.2003.1240952"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.2003.1240952","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2003.1240952","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 21st International Conference on Computer Design","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5065567362","display_name":"M. Dall'Osso","orcid":null},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"M. Dall'Osso","raw_affiliation_strings":["DEIS, University of Bologna, Bologna, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"DEIS, University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016918484","display_name":"G. Biccari","orcid":null},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"G. Biccari","raw_affiliation_strings":["DEIS, University of Bologna, Bologna, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"DEIS, University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081786807","display_name":"L. Giovannini","orcid":null},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"L. Giovannini","raw_affiliation_strings":["DEIS, University of Bologna, Bologna, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"DEIS, University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5011268330","display_name":"Davide Bertozzi","orcid":"https://orcid.org/0000-0001-7462-4551"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"D. Bertozzi","raw_affiliation_strings":["DEIS, University of Bologna, Bologna, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"DEIS, University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5082872202","display_name":"L. Benini","orcid":null},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"L. Benini","raw_affiliation_strings":["DEIS, University of Bologna, Bologna, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"DEIS, University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I9360294"],"apc_list":null,"apc_paid":null,"fwci":4.0206,"has_fulltext":false,"cited_by_count":76,"citation_normalized_percentile":{"value":0.94968259,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"536","last_page":"539"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.982699990272522,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9812999963760376,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8129664063453674},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.6653304696083069},{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.6417670845985413},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.6312629580497742},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6129521727561951},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5818426609039307},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5261513590812683},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.47980788350105286},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.4757744371891022},{"id":"https://openalex.org/keywords/network-interface","display_name":"Network interface","score":0.46700629591941833},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.45779329538345337},{"id":"https://openalex.org/keywords/parameterized-complexity","display_name":"Parameterized complexity","score":0.4220256209373474},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3491789698600769},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.25796401500701904},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.10628631711006165}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8129664063453674},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.6653304696083069},{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.6417670845985413},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.6312629580497742},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6129521727561951},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5818426609039307},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5261513590812683},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.47980788350105286},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.4757744371891022},{"id":"https://openalex.org/C103987645","wikidata":"https://www.wikidata.org/wiki/Q985806","display_name":"Network interface","level":3,"score":0.46700629591941833},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.45779329538345337},{"id":"https://openalex.org/C165464430","wikidata":"https://www.wikidata.org/wiki/Q1570441","display_name":"Parameterized complexity","level":2,"score":0.4220256209373474},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3491789698600769},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.25796401500701904},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.10628631711006165},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C172173386","wikidata":"https://www.wikidata.org/wiki/Q79984","display_name":"Ethernet","level":2,"score":0.0},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iccd.2003.1240952","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2003.1240952","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 21st International Conference on Computer Design","raw_type":"proceedings-article"},{"id":"pmh:oai:iris.unife.it:11392/1192667","is_oa":false,"landing_page_url":"http://hdl.handle.net/11392/1192667","pdf_url":null,"source":{"id":"https://openalex.org/S4306400369","display_name":"Institutional Research Information System University of Ferrara (University of Ferrara)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I201324441","host_organization_name":"University of Ferrara","host_organization_lineage":["https://openalex.org/I201324441"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.6399999856948853}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2033923590","https://openalex.org/W2376124569","https://openalex.org/W2372348522","https://openalex.org/W2135667768","https://openalex.org/W2517347894","https://openalex.org/W2387047473","https://openalex.org/W2114015630","https://openalex.org/W4230458348","https://openalex.org/W3198758847","https://openalex.org/W1581055755"],"abstract_inverted_index":{"The":[0,49,64],"growing":[1],"complexity":[2],"of":[3,35,51,72,86],"customizable":[4],"embedded":[5],"multiprocessor":[6,32],"architectures":[7],"for":[8,31,104],"digital":[9],"media":[10],"processing":[11],"will":[12],"soon":[13],"require":[14],"highly":[15],"scalable":[16,26],"network-on-chip":[17],"based":[18],"communication":[19,103],"infrastructures.":[20],"Here,":[21],"we":[22],"propose":[23],"xpipes,":[24],"a":[25,83],"and":[27,61,100,122],"high-performance":[28],"NoC":[29,56],"architecture":[30],"SoCs,":[33],"consisting":[34],"soft":[36],"macros":[37],"that":[38],"can":[39,79],"be":[40,80],"turned":[41],"into":[42],"instance-specific":[43],"network":[44,74],"components":[45,53],"at":[46,69,119],"instantiation":[47],"time.":[48],"flexibility":[50],"its":[52],"allows":[54],"our":[55],"to":[57,88],"support":[58,101],"both":[59],"homogeneous":[60],"heterogeneous":[62],"architectures.":[63],"interface":[65],"with":[66,82],"IP":[67],"cores":[68],"the":[70,73,120],"periphery":[71],"is":[75],"standardized":[76],"(OCP-based).":[77],"Links":[78],"pipelined":[81],"flexible":[84],"number":[85],"stages":[87],"decouple":[89],"data":[90],"introduction":[91],"speed":[92],"from":[93],"worst-case":[94],"link":[95,106],"delay.":[96],"Switches":[97],"are":[98],"lightweight":[99],"reliable":[102],"arbitrary":[105],"pipeline":[107],"depths":[108],"(latency":[109],"insensitive":[110],"operation).":[111],"Xpipes":[112],"has":[113],"been":[114],"described":[115],"in":[116],"synthesizable":[117],"SystemC,":[118],"cycle-accurate":[121],"signal-accurate":[123],"level.":[124]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":2},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":8}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
