{"id":"https://openalex.org/W2113738958","doi":"https://doi.org/10.1109/iccd.2003.1240917","title":"Interconnect estimation for FPGAs under timing driven domains","display_name":"Interconnect estimation for FPGAs under timing driven domains","publication_year":2004,"publication_date":"2004-05-06","ids":{"openalex":"https://openalex.org/W2113738958","doi":"https://doi.org/10.1109/iccd.2003.1240917","mag":"2113738958"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.2003.1240917","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2003.1240917","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 21st International Conference on Computer Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5112222457","display_name":"Parivallal Kannan","orcid":null},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Parivallal Kannan","raw_affiliation_strings":["Center for Integrated Circuits and Systems, University of Texas, Dallas, Richardson, TX, USA","Center for Integrated Circuits & Syst., Texas Univ., Richardson, TX, USA"],"affiliations":[{"raw_affiliation_string":"Center for Integrated Circuits and Systems, University of Texas, Dallas, Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]},{"raw_affiliation_string":"Center for Integrated Circuits & Syst., Texas Univ., Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5079171474","display_name":"Dinesh Bhatia","orcid":"https://orcid.org/0000-0001-5412-8868"},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dinesh Bhatia","raw_affiliation_strings":["Center for Integrated Circuits and Systems, University of Texas, Dallas, Richardson, TX, USA","Center for Integrated Circuits & Syst., Texas Univ., Richardson, TX, USA"],"affiliations":[{"raw_affiliation_string":"Center for Integrated Circuits and Systems, University of Texas, Dallas, Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]},{"raw_affiliation_string":"Center for Integrated Circuits & Syst., Texas Univ., Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5112222457"],"corresponding_institution_ids":["https://openalex.org/I162577319"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.16018722,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"220","issue":null,"first_page":"344","last_page":"349"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.8014870882034302},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.730102002620697},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.676254153251648},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.6645156145095825},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6561930179595947},{"id":"https://openalex.org/keywords/suite","display_name":"Suite","score":0.5766783952713013},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.5239289402961731},{"id":"https://openalex.org/keywords/estimation","display_name":"Estimation","score":0.4431770145893097},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.3929210901260376},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3820491433143616},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.26765263080596924},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17124614119529724},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.1619763970375061},{"id":"https://openalex.org/keywords/systems-engineering","display_name":"Systems engineering","score":0.0940503180027008}],"concepts":[{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.8014870882034302},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.730102002620697},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.676254153251648},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.6645156145095825},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6561930179595947},{"id":"https://openalex.org/C79581498","wikidata":"https://www.wikidata.org/wiki/Q1367530","display_name":"Suite","level":2,"score":0.5766783952713013},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.5239289402961731},{"id":"https://openalex.org/C96250715","wikidata":"https://www.wikidata.org/wiki/Q965330","display_name":"Estimation","level":2,"score":0.4431770145893097},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.3929210901260376},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3820491433143616},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.26765263080596924},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17124614119529724},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.1619763970375061},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0940503180027008},{"id":"https://openalex.org/C166957645","wikidata":"https://www.wikidata.org/wiki/Q23498","display_name":"Archaeology","level":1,"score":0.0},{"id":"https://openalex.org/C95457728","wikidata":"https://www.wikidata.org/wiki/Q309","display_name":"History","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccd.2003.1240917","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2003.1240917","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 21st International Conference on Computer Design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":29,"referenced_works":["https://openalex.org/W1508968487","https://openalex.org/W1556480701","https://openalex.org/W1578824783","https://openalex.org/W1585249527","https://openalex.org/W1597088765","https://openalex.org/W1989060364","https://openalex.org/W1991530123","https://openalex.org/W2005314985","https://openalex.org/W2015540924","https://openalex.org/W2020112047","https://openalex.org/W2024060531","https://openalex.org/W2063781085","https://openalex.org/W2065217265","https://openalex.org/W2092883699","https://openalex.org/W2110265185","https://openalex.org/W2111104699","https://openalex.org/W2116021187","https://openalex.org/W2139637699","https://openalex.org/W2147657819","https://openalex.org/W2153580689","https://openalex.org/W2160533909","https://openalex.org/W2178873339","https://openalex.org/W2275304190","https://openalex.org/W2911302472","https://openalex.org/W4234192746","https://openalex.org/W4253028153","https://openalex.org/W6666545738","https://openalex.org/W6677370016","https://openalex.org/W6683655027"],"related_works":["https://openalex.org/W2026822479","https://openalex.org/W2082487009","https://openalex.org/W1859946853","https://openalex.org/W2976181145","https://openalex.org/W2030852227","https://openalex.org/W2129468521","https://openalex.org/W4253016735","https://openalex.org/W2409361203","https://openalex.org/W2146757344","https://openalex.org/W4256147002"],"abstract_inverted_index":{"Interconnect":[0],"planning":[1,19],"is":[2,20,75],"fast":[3],"becoming":[4],"an":[5],"important":[6],"design":[7,82,137],"issue":[8],"for":[9,17,35,55],"large":[10],"FPGA":[11,38,109],"based":[12],"designs.":[13],"The":[14],"fundamental":[15],"requirement":[16],"interconnect":[18,53,70,105],"the":[21,25,48,52,69,104,120,130],"ability":[22],"to":[23,94,102],"estimate":[24,103],"routing":[26,87,122,127],"requirements":[27,54,72,106],"of":[28,50,76,107],"a":[29,99],"given":[30],"design.":[31,59],"Many":[32],"estimation":[33,45,61],"methods":[34,62],"uniform":[36],"island-style":[37],"architectures":[39],"have":[40],"been":[41],"reported.":[42],"However,":[43],"no":[44],"method":[46,101],"targets":[47],"problem":[49],"estimating":[51],"timing":[56,74,112],"driven":[57,80,113],"physical":[58,81],"Most":[60],"assume":[63],"minimum":[64,85],"cost":[65],"routing,":[66],"which":[67,88],"underestimates":[68],"resource":[71],"when":[73],"main":[77],"concern.":[78],"Timing":[79],"typically":[83],"involves":[84],"delay":[86],"demands":[89],"extra":[90],"interconnects":[91],"as":[92],"compared":[93],"minimum-cost":[95],"routing.":[96],"We":[97,115],"propose":[98],"new":[100],"placed":[108],"circuits,":[110],"under":[111],"domains.":[114],"compare":[116],"our":[117],"estimates":[118],"with":[119],"detailed":[121],"results":[123],"produced":[124],"by":[125],"standard":[126],"tools":[128],"in":[129],"VPR":[131],"[V.":[132],"Betz":[133],"et":[134],"al.,":[135],"(1997)]":[136],"suite.":[138]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}