{"id":"https://openalex.org/W2145955897","doi":"https://doi.org/10.1109/iccd.2003.1240916","title":"Non-crossing OBDDs for mapping to regular circuit structures","display_name":"Non-crossing OBDDs for mapping to regular circuit structures","publication_year":2004,"publication_date":"2004-05-06","ids":{"openalex":"https://openalex.org/W2145955897","doi":"https://doi.org/10.1109/iccd.2003.1240916","mag":"2145955897"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.2003.1240916","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2003.1240916","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 21st International Conference on Computer Design","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111659833","display_name":"A. Cao","orcid":null},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"A. Cao","raw_affiliation_strings":["School of Electrical, Purdue University, West Lafayette, IN"],"affiliations":[{"raw_affiliation_string":"School of Electrical, Purdue University, West Lafayette, IN","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110204557","display_name":"Cheng\u2010Kok Koh","orcid":null},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"C.-K. Koh","raw_affiliation_strings":["School of Electrical, Purdue University, West Lafayette, IN, USA"],"affiliations":[{"raw_affiliation_string":"School of Electrical, Purdue University, West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5111659833"],"corresponding_institution_ids":["https://openalex.org/I219193219"],"apc_list":null,"apc_paid":null,"fwci":1.6939,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.84986162,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":96,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"338","last_page":"343"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.6295217275619507},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.6084882020950317},{"id":"https://openalex.org/keywords/boolean-function","display_name":"Boolean function","score":0.5939313173294067},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5856110453605652},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5562178492546082},{"id":"https://openalex.org/keywords/binary-decision-diagram","display_name":"Binary decision diagram","score":0.5415568351745605},{"id":"https://openalex.org/keywords/data-structure","display_name":"Data structure","score":0.48105621337890625},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.47838249802589417},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4541094899177551},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3331971764564514},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.08723422884941101},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.06893914937973022}],"concepts":[{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.6295217275619507},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.6084882020950317},{"id":"https://openalex.org/C187455244","wikidata":"https://www.wikidata.org/wiki/Q942353","display_name":"Boolean function","level":2,"score":0.5939313173294067},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5856110453605652},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5562178492546082},{"id":"https://openalex.org/C3309909","wikidata":"https://www.wikidata.org/wiki/Q864155","display_name":"Binary decision diagram","level":2,"score":0.5415568351745605},{"id":"https://openalex.org/C162319229","wikidata":"https://www.wikidata.org/wiki/Q175263","display_name":"Data structure","level":2,"score":0.48105621337890625},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.47838249802589417},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4541094899177551},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3331971764564514},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.08723422884941101},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.06893914937973022},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iccd.2003.1240916","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2003.1240916","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings 21st International Conference on Computer Design","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.151.2497","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.151.2497","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://dynamo.ecn.purdue.edu/~chengkok/papers/2003/p338-cao.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/16","display_name":"Peace, Justice and strong institutions","score":0.46000000834465027}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W37898813","https://openalex.org/W141882208","https://openalex.org/W1496641256","https://openalex.org/W1989804605","https://openalex.org/W2110790180","https://openalex.org/W2117043478","https://openalex.org/W2129393085","https://openalex.org/W2144491553","https://openalex.org/W4239400817","https://openalex.org/W6601587724","https://openalex.org/W6605809003","https://openalex.org/W6629585307"],"related_works":["https://openalex.org/W257150968","https://openalex.org/W3140601928","https://openalex.org/W1977451125","https://openalex.org/W2057159994","https://openalex.org/W2168881618","https://openalex.org/W1608751818","https://openalex.org/W86917440","https://openalex.org/W2133491672","https://openalex.org/W2109998394","https://openalex.org/W4389483408"],"abstract_inverted_index":{"We":[0,45],"propose":[1],"a":[2,18,52],"novel":[3],"compact":[4],"BDD":[5,10],"structure,":[6],"called":[7],"noncrossing":[8],"ordered":[9],"(NCOBDD),":[11],"that":[12,50,63],"can":[13],"be":[14],"mapped":[15],"directly":[16],"to":[17,56],"regular":[19,26],"circuit":[20],"structure.":[21],"Compared":[22],"with":[23,83],"other":[24],"BDD-based":[25],"structures,":[27],"NCOBDD-mapped":[28],"circuits":[29],"reduce":[30],"the":[31,40,43,68],"costs":[32],"of":[33,42],"area,":[34,72],"power":[35,73],"and":[36,74,79],"latency,":[37],"while":[38],"preserving":[39],"regularity":[41],"structures.":[44],"also":[46],"present":[47],"an":[48],"algorithm":[49],"uses":[51],"top-down":[53],"level-by-level":[54],"sweep":[55],"construct":[57],"minimal":[58],"NCOBDDs.":[59],"Experimental":[60],"results":[61],"show":[62],"for":[64],"asymmetric":[65],"benchmark":[66],"circuits,":[67],"average":[69],"reduction":[70],"on":[71],"latency":[75],"are":[76],"61.6%,":[77],"53.1%":[78],"69.2%,":[80],"respectively,":[81],"compared":[82],"yet":[84],"another":[85],"decision":[86],"diagram":[87],"(YADD)":[88],"[A.":[89],"Mukherjee":[90],"et":[91],"al.,":[92],"(1999)].":[93]},"counts_by_year":[{"year":2013,"cited_by_count":3}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}